Accelerator Power Management and Debug Microarchitecture & Logic Design Lead

Rivos is developing industry-leading server solutions that combine power efficiency, high performance, and security, built on RISC-V and designed with workload-defined hardware. We are seeking an expert in power management and Debug architecture to join our team in building the best hardware in the world.

Responsibilities

• Develop microarchitecture specifications for power management and debug features
• Own the RTL development of power management and debug features
• Work with verification, physical implementation, DFT, and firmware teams to deliver a design which meets functional, performance, and power requirements
• Work with external IP vendors to evaluate and integrate IP into the design
• Work with the SoC and PD teams to deliver final RTL for supporting the clock, reset, and various debug features
• Use domain knowledge to propose and evaluate new features

Requirements

• Knowledge of modern GPU or CPU microarchitectures
• 5+ years of relevant industry experience in power management
• Knowledge of synchronous and asynchronous reset flows, as well as clock and reset domain crossing
• Knowledge or experience with active and idle power management techniques
• Proficient in SystemVerilog and Python
• Knowledge or experience with Debug and Trace infrastructure
• Prior experience with DFT and PD is a plus but not required
• Knowledge of GPU architecture is a plus but not required

Education

Bachelor’s, Master’s or PhD in EE or ECE