Coherent Interconnect Microarchitecture & Logic Design - Full Time

3 Months ago • All levels • Research & Development • Undisclosed

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Job Description

Rivos is seeking Interconnect/Fabric Design experts with extensive knowledge of on-chip coherent/non-coherent interconnect architecture, AMBA/AXI/CHI/ACE/Tilelink/APB protocols, cache coherent memory systems, and system caches. Experience in high performance and low power microarchitecture techniques and RTL coding using SystemVerilog/Verilog is essential.

Must have:

Interconnect Architecture
On-chip Protocols
Cache Coherent
RTL Coding

Good to have:

System Caches
Network Topologies
Microarchitecture Techniques
Waveform Debugging

Rivos is on a mission to build the best RISC-V enterprise systems in the world with class leading performance, power, security and RAS features. We are seeking Interconnect/Fabric Design experts to join our team in building the best RISC-V compute systems in the world.

Responsibilities

Microarchitecture development and specification - from early high-level architectural exploration through micro architectural research and arriving at a detailed specification
Development, assessment, and refinement of RTL design to target power, performance, area, and timing goals
Validation - support test bench development and simulation for functional and performance verification
Performance exploration and correlation - explore high performance strategies and validate that the RTL design meets targeted performance
Design delivery - work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and power

Requirements

Thorough knowledge of large scale on-chip coherent or non-coherent interconnect/fabric architecture
Knowledge of one or more on-chip network protocols: AMBA, AXI, CHI, ACE, Tilelink, APB or similar protocols
Knowledge of cache coherent memory systems and interconnect
Knowledge of system caches and directory snoop filter protocols
Familiarity with different on-chip network topologies: mesh, ring, crossbar, etc
Understanding of high performance and low power microarchitecture techniques and trade-offs
Proficiency in SystemVerilog or Verilog RTL coding
Knowledge of logic design principles along with timing and power implications
Experience with simulators and waveform debugging tools

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