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Who We Are
We are working on the CPU design in Folsom. The team in Folsom has the frontend team working on ucode, RTL and validation. We also have a backend team working on circuit design, structural design, low power design. Finally, we have a backend integration working on full-chip timing, layout and design integration.
Who You Are
Responsibilities include but are not limited to:
Develops the logic design, register transfer level (RTL) coding, and simulation for a CPU required to generate cell libraries, functional units, and the CPU IP block for integration in full chip designs.
Participates actively in the definition of architecture and microarchitecture features of the CPU being designed.
Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
Documents micro architectural specs (MAS) of the CPU features being designed. Supports SoC customers to ensure high-quality integration of the CPU block.
You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
Bachelor's degree in Electrical/Computer Engineering or Computer Science and 4+ years of experience or a Master's degree in Electrical/Computer Engineering or Computer Science and 3+ years of experience.
3+ combined experience in:
System Verilog/Verilog/VHDL and/or VCS or similar Simulator
Logic design and/or front end.
Computer architecture and microarchitecture.
Software/programming languages (i.e. C, C++, C#, Visual Basic/.NET. Perl, Python, Java, etc.).
Modern energy-efficient/low-power logic design techniques, including those specifically applicable to high frequency optimization.
Preferred Qualifications
Knowledge of Intel Architecture ISA and system architecture, including x86 assembly language.
Experience with high-speed circuit design and optimization for Datapath, circuits and/or arrays.
Familiarity with circuit planning and timing convergence.
Experience working with cross functional teams (Architecture, Spec development, Design, Formal, Verification).
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003
Annual Salary Range for jobs which could be performed in the US:
$161,230.00-$227,620.00Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.Intel provides reasonable accommodation to applicants and employees. For more information on our Reasonable Accommodation process, please clickhere.When you use this site, Intel Corporation uses cookies to improve your online experience. For more information, visit ourCookie Notice.To view our candidate privacy notice, please clickhere.
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