This role involves conceptualizing, documenting, and designing tools, flows, and methods (TFM) for verifying IPs and SOCs, including their interaction and reuse. The engineer will drive verification methodologies, develop test and coverage plans, and create test bench components for efficient execution. Key responsibilities include analyzing quality gaps to improve existing TFM, supporting verification environment development (stimulus, checkers, assertions, coverage), and collaborating with design verification engineers to enhance methodologies for better quality and performance.

Must Have

• Familiarity working in UNIX environments
• Proficiency with frontend simulation tools (VCS, Verdi, coverage tools)
• Strong scripting skills (Python, Perl, shell scripting, or similar)
• Experience in simulation debug techniques and methodologies
• Excellent problem-solving abilities with demonstrated independence in finding and verifying solutions
• Strong interpersonal and communication skills
• Ability to work collaboratively in a team environment

Good to Have

• Experience working with IT requirements for LSF, Disk Usage, Memory Requirements, etc
• Experience working with SoC Verification Methodologies and UVM based verification environments. Test Bench bring-up at SoC and strong programming skills in System Verilog, OVM and UVM.
• Test Plan development experience.
• Enabling regressions, maintaining QoV (quality of validation) with good functional/code/other coverage metrics.
• Familiarity with both simulation and emulation environments.
• Strong CPU/GPU architecture understanding.
• RTL Debugging module level or soc level system simulation failures.
• Building emulation models, enabling content
• Working with Validation Engineers and central CAD teams to support and maintain verification requirements in terms of Automation and tool flow support.
• Coordinating with Val team on CAD Requirement with support CAD, IT and Engineering Compute Teams.
• Act as focal point between design and tool vendors for issues and feature enhancements.
• Training/Supporting Validation Engineers in CAD tool flow and Infrastructure
• Monitoring and improve existing simulation environments and simulation efficiency.

Perks & Benefits

• Hybrid work model

Job Description:

Conceptualizes, documents, and designs tools, flows, and methods (TFM) for use in the verification of IPs, SOCs, and the interaction/handoff/reuse between IPs and SOCs. Drives verification methodologies that allow planning and execution and develops test, coverage plans, and test bench components to enable effective and efficient execution. Analyzes retrospective data on current generation quality and efficiency gaps to identify proper incremental, evolutionary, or transformative changes to the existing verification TFM. Supports development of verification environment, including components such as stimulus, checkers, assertions, trackers, and coverage. Works with design verification engineers to create and enhance verification methodologies for improving quality and performance.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Bachelor's degree in electrical engineering or computer engineering with 5+ years of experience or a master's degree in electrical engineering or computer engineering with 3+ years of industry experience

Required Qualifications:

• Familiarity working in UNIX environments
• Proficiency with frontend simulation tools (VCS, Verdi, coverage tools)
• Strong scripting skills (Python, Perl, shell scripting, or similar)
• Experience in simulation debug techniques and methodologies
• Excellent problem-solving abilities with demonstrated independence in finding and verifying solutions
• Strong interpersonal and communication skills
• Ability to work collaboratively in a team environment

Preferred Qualifications:

1. Experience working with IT requirements for LSF, Disk Usage, Memory Requirements, etc

2. Experience working with SoC Verification Methodologies and UVM based verification environments. Test Bench bring-up at SoC and strong programming skills in System Verilog, OVM and UVM.

3. Test Plan development experience.

4. Enabling regressions, maintaining QoV (quality of validation) with good functional/code/other coverage metrics.

5. Familiarity with both simulation and emulation environments.

6. Strong CPU/GPU architecture understanding.

7. RTL Debugging module level or soc level system simulation failures.

8. Building emulation models, enabling content

9. Working with Validation Engineers and central CAD teams to support and maintain verification requirements in terms of Automation and tool flow support.

10. Coordinating with Val team on CAD Requirement with support CAD, IT and Engineering Compute Teams.

11. Act as focal point between design and tool vendors for issues and feature enhancements.

12. Training/Supporting Validation Engineers in CAD tool flow and Infrastructure

13. Monitoring and improve existing simulation environments and simulation efficiency.