DSP or Serdes RTL Senior Principal Digital Design Engineer

2 Months ago • 10 Years + • $154,000 PA - $286,000 PA

Software Development & Engineering

Job Description

This role involves joining a dynamic team focused on developing high-speed PMA layer IP for industry-standard protocols. The engineer will be responsible for front-end coding, scripting, and developing flows throughout the digital design and functional verification phases. Collaboration with digital, analog, and application teams is expected. The position requires a strong background in DSP and Serdes, with experience in RTL logic design, debug, and functional verification. Understanding of digital architecture trade-offs, clock domain crossings, synthesis, static timing analysis, and physical design flows is also crucial. Excellent communication and organizational skills are necessary. Experience with FPGA, emulation, and firmware development is a plus. Substantial Verilog experience and strong logic/debug skills are required.

Good To Have:

Strong background in DSP and algorithms
Familiarity with Ethernet PMA/PMD/PCS layers
Understanding of mixed-signal design impact on digital flows
Experience with FPGA and/or emulation platforms
Firmware development of embedded microcontroller systems
Ethernet connectivity protocol knowledge
Mixed-signal IP development procedures

Must Have:

At least 10 years of work experience in SerDes
Thorough understanding of end-to-end digital design flow
Digital microarchitecture definition and documentation
RTL logic design, debug, and functional verification
Understanding of digital architecture trade-offs (power, performance, area)
Understanding of asynchronous clock domain crossings
Understanding of Lint checks and error resolution
Understanding of synthesis timing constraints and static timing analysis
Understanding of fundamental physical design flows
Excellent communication skills
Self-motivated and well-organized
Substantial experience with Verilog
Excellent logic and debug skills

Perks:

Incentive compensation (bonus, equity)
Paid vacation
Paid holidays
401(k) plan with employer match
Employee stock purchase plan
Medical, dental, and vision plan options

Add these skills to join the top 1% applicants for this job

communication

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

This is an opportunity to join a dynamic and growing team of engineers developing high-speed PMA layer IP for industry-standard protocols. The successful candidate will be a highly self-motivated and results-oriented member of a small team of engineers that can learn and improve existing digital flows. The candidate will primarily be responsible for front-end coding, scripting and developing flows at all phases of the digital design and functional verification. It is further expected that the candidate will be able to work as part of a small and focused team of engineers and will be able to collaborate successfully as needed with the digital, analog and application teams. Candidate should be willing to work full time in the San Jose office. A Cadence satellite office (if senior with extensive SerDes exp.) will be considered.

Position Requirements

This team is focused on DSP and/or High Speed Serdes. The ideal candidate will have at least 10 plus years of actual work experience in SerDes as well as a thorough understanding of the end-to-end digital design flow in order to accurately and efficiently collaborate with all members of the technical staff, both analog and digital, regarding overall project development progress and status. This includes but is not limited to:

Digital microarchitecture definition and documentation
RTL logic design, debug and functional verification
Strong background in DSP and algorithms is a plus.
Familiar with the PMA/PMD/PCS layers of the Ethernet protocol is a plus.
Understanding of digital architecture trade-offs for power, performance, and area
Understanding of proper handling of multiple asynchronous clock domains and their crossings
Understanding of Lint checks and proper resolution of errors
Understanding synthesis timing constraints, static timing analysis and constraint development
Understanding of fundamental physical design flows and stages
Understanding impacts of analog and mixed-signal design and verification on digital-on-top development flow.
Exhibit excellent communication skills and be self-motivated and well organized.
Experience with FPGA and/or emulation platform is a plus.
Firmware development of embedded microcontroller systems is a plus.

Substantial experience with Verilog is required, as are excellent logic and debug skills. Engineering expertise in mixed-signal IP development procedures and Ethernet connectivity protocol knowledge are also strongly preferred.

#LI-MA1

The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.