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GPU Functional Verification Engineer

In the role of GPU Functional Verification Engineer, your project responsibilities will include the following,

• Develop deep understanding of 3-D Graphics hardware pipeline, feature sets, data paths, block functionalities & interfaces
• Strategize, brainstorm, and propose a DV environment, develop test bench, own test plan, debug all RTL artefacts, and achieve all signoff matrices
• Engage with EDA vendors, explore new and innovative DV methodologies to push the limits of sign off quality
• Collaborate with worldwide architecture, design, and systems teams to achieve all project goals
• Currently, we are looking for candidates who can match one or more of the profiles listed below,
• Strong knowledge of UVM based System Verilog TB Knowledge of GPU pipeline design is a plus, not mandatory Proficiency with formal tools – working knowledge of Property based FV is a plus, not mandatory Strong communication skills (both written and verbal) Most importantly, ability to learn, improve and deliver

 
The pre-Si verification team in Bangalore is currently heavily involved in the following

• UVM/SV based constrained random test bench for functional verification
• Subsystem level TB for complete GPU workload analysis and compliance
• Emulation platforms to analyze performance and pipeline bottlenecks
• Formal tools – both for reduced time to bug & property based FV sign-off
• Power Aware & Gate level simulations to deliver a high-quality GPU implementation
• Perl/Python scripts for automation in managing regressions, optimize run time, manage database and bug

Minimum Qualifications:

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