GPU Physical Design Engineer- Floorplanning

Company:

Job Area:

General Summary:

This position centers on floor-planning expertise at both block and top levels for industry-leading graphics core designs, with a strong emphasis on scalability and achieving aggressive Power, Performance, and Area (PPA) targets. The role involves working on cutting-edge technology nodes and applying advanced physical design techniques to push the boundaries of GPU performance and efficiency. This role is open in either San Diego or Austin location.

Key responsibilities include:

• Driving floorplan architecture and optimization in collaboration with RTL and architecture teams to maximize PPA
• Engaging in cross-functional collaboration with verification, timing, power, and packaging teams to ensure holistic design convergence
• Partnering with EDA tool vendors and internal CAD teams to develop and enhance automation flows and methodologies for improved design efficiency
• Making strategic trade-offs in design decisions to achieve optimal PPA outcomes while maintaining schedule and quality targets

The ideal candidate will have/demonstrate the following:

• Experience in Physical design which includes floor-planning, placement, clock implementation, routing for complex, big and high frequency designs
• Experience with physical synthesis and implementation tools - Synopsys Fusion Compiler, ICC2 and Cadence Genus/Innovus
• Must have good knowledge of static timing analysis, reliability and power analysis
• Strong understanding of CMOS circuit design and design techniques to push Power, Performance and Area of complex designs
• Ability to think outside the box for innovative solutions to improve power and eliminate performance bottlenecks
• Strong understanding of GPU micro-architecture and collaborate with RTL designers to improve bottlenecks for power and performance
• Solid working knowledge of scripting skills including tcl, perl or python
• Excellent communication skills and collaborating in a team environment is a must

Preferred Skills:

• Clock implementation, power delivery network design choices, process technology, prior experience in flow and methodology development, block closure
• Close interaction with design and architecture teams to influence scalable floor-plans and optimal bus/pin/repeater planning for entire IP and its sub-blocks
• Hands on experience with Synthesis, DFT, Place and Route, Timing and Reliability Signoff
• Hands on experience working with very complex designs that push the envelope of Power, Performance and Area
• Hands on experience working with sub-micron technology process nodes eg. 5nm, 4nm and below is highly advantageous
• Prior experience in flow and methodology development is an advantage
• Excellent debug and analytical skills and demonstrated successes in floor-planning large IP and high frequency designs
• Ability to drive Physical Implementation teams in Floor-planning and work well in a collaborative environment with multi-disciplined teams

Minimum Qualifications:

• Bachelor’s degree in Electrical/Computer Engineering
• 8+ years of direct top level floor-planning large and high frequency IP experience which includes bus/pin/repeater planning at the top level
• Strong background in VLSI design, physical implementation and scripting
• Strong background and experience working with industry standard Synthesis and Place and Route tools including Signoff tools
• Hands on experience taping out designs in sub-micron technology node design < 10nm
• Expect strong self-motivation and time management skills

Preferred Qualifications:

• Master’s degree in Electrical/Computer Engineering
• 8+ years of direct top level floor-planning large and high frequency IP experience
• In depth end to end experience from RTL2GDS, taping out at least 6 complex designs
• Direct hands on experience with bus/pin/repeater planning for entire IP

Minimum Qualifications:

To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.

EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

Pay range and Other Compensation & Benefits:

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm.  We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus).  In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.

If you would like more information about this role, please contact Qualcomm Careers.