High Speed SerDes DSP RTL Designer

Broadcom is looking for a high-speed DSP SerDes RTL designer. Qualifications include:

• MS or PhD in Electrical Engineering or Computer Engineering with 6+ years of experience in high speed ADC based SerDes RTL design.
• Proficient with Verilog-HDL/System Verilog coding for PAM4 DSP based SerDes including equalization, adaptation and high-speed ADC calibration.
• Proficient with front end tools such as NCVerilog, NCSIM, Simvision, Lint.
• Exposure to Design for test, understanding of scan concept and writing DFT friendly RTL.
• Deep understanding of high-speed serial interconnect architectures such as 100G/200G per lane PAM4 and design trade-offs to drive attainment on metrics such as performance, power, and cost over the project lifetime.
• Experience in synthesis, CDC, static timing analysis.
• Exposure to SDF annotated simulations with good understanding of parasitic delays.
• Experience in design management with detailed knowledge of development methodologies, design flows including EDA integration, foundry PDK and associated collaterals.
• Strong analytical thinking and problem-solving skills with excellent attention to details.
• Must be organized, self-motivated and able to work effectively across internal and end customers teams.
• Must have excellent knowledge/experience with TSMC 7nm-2nm, i.e. understanding of power consumptions, area, estimated design and layout efforts for digital and analog blocks, technology limitations.

Highly Desired Qualifications:

• Understanding of micro architecture with standard peripherals such as AMBA BUS/I2C/SPI/UART.
• Deep understanding of Signal Integrity and Power Integrity modeling for High Speed designs.
• Understanding & exposure to verilog AMS simulation, experience in behavioral models of analog circuit will be helpful.