IC Power, IR and EM Sr. Application Engineer

4 Months ago • All levels • $84,000 PA - $156,000 PA

Software Development & Engineering

Job Description

Cadence is looking for a Senior Application Engineer to solve complex challenges in chip power integrity and thermal analysis. The ideal candidate should possess strong analytical skills to solve electrical and electronic circuits, along with an understanding of power, IR, and EM analyses, and chip planning. The role involves expertise in interconnect modeling, package analysis, and die modeling, as well as experience in writing and debugging automation code in Python or Tcl. The ability to grasp foundational algorithms, along with familiarity with the EDA and Semiconductor industry ecosystem, and teamwork are also required.

Must Have:

Solve electrical and electronic circuits
Knowledge of power, IR, and EM analyses
Understanding of interconnect modeling
Ability to write automation code in Python/Tcl
Understanding of EDA and Semiconductor industry

Perks:

Paid vacation and paid holidays
401(k) plan with employer match
Employee stock purchase plan
Medical, dental and vision plan options

Add these skills to join the top 1% applicants for this job

team-player

unity

data-structures

python

algorithms

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

At Cadence, you have the opportunity to work with the dynamic and tenacious team solving some of the most complicated challenges in chip power integrity and thermal analysis. We are looking for people that are willing to push the boundaries of innovation to deliver highest quality solutions to our customers.
If tenacity, passion to innovate, determination to collaborate effectively, and win as a team are the attributes that define you, then you have a home in our Multi-physics System Analysis team solving Power Integrity problems.

Ideal candidate should have:

Strong ability to solve electrical and electronic circuits.
Excellent knowledge on how power, IR, and EM analyses impact chip planning to IR/EM sign-off.
Fundamental understanding of interconnect modeling, package analysis, and die modeling.
Ability to write and debug automation code in Python or Tcl.
Solid grasp on foundational algorithms to solve numerical and graph problems.
Basic idea on how EDA and Semiconductor industry eco-system works.
Alacrity to be an excellent team player.

The annual salary range for California is $84,000 to $156,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.