Ph.D. Candidate in Functional Safety for AI Accelerators - Contract Duration 3 Years (f/m/d)

8 Minutes ago • All levels

Research Development

Job Description

Cadence is seeking a highly motivated PhD candidate for the TIRAMISU project, focusing on functional safety for AI accelerators. The role involves identifying safety-critical components, developing advanced safety analysis methodologies, and optimizing safety verification techniques like simulation-based fault injection and formal verification. The goal is to integrate these methods into Cadence’s functional safety toolchain to improve verification processes and accelerate time-to-market for AI accelerators, aligning with ISO 26262 standards.

Good To Have:

A background in functional safety is desirable

Must Have:

MSc (or equivalent) in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline
Solid understanding of digital IC design and verification methodologies
Proficiency in hardware description languages (e.g., Verilog, VHDL) and programming
Fulfill the eligibility rules mentioned on the project website and the Ph.D. requirements of the TU Delft
Apply for the TIRAMISU (DC2.4) position using the provided link

Perks:

Competitive Salary
30 days annual leave
Meal vouchers
Capital Forming Payment (VwL)
Ticket for the public transport
Working in a hybrid model in a modern office concept

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game-texts

We are looking for a highly motivated PhD candidate to join the TIRAMISU project (Training and Innovation in Reliable and Efficient Chip Design for Edge AI, https://tiramisu-project.eu/).

The research will focus on the functional safety aspects of AI accelerators, aligned with ISO 26262 standards and utilizing state-of-the-art EDA tools. The PhD work will involve identifying safety-critical components of AI accelerators and developing advanced safety analysis methodologies.

The goal is to develop safety mechanisms and optimize safety verification techniques, including simulation-based fault injection and formal verification, to enhance the safety of AI hardware. These methods will be integrated into Cadence’s functional safety toolchain, contributing to a novel methodology that improves safety verification processes and accelerates time-to-market for AI accelerators.

Required qualifications:

MSc (or equivalent) in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline
Solid understanding of digital IC design and verification methodologies
Proficiency in hardware description languages (e.g., Verilog, VHDL) and programming
A background in functional safety is desirable

Requirements:

The applicant must fulfil the eligibility rules mentioned on the project website (https://tiramisu-project.eu/vacancies/eligibility) and the Ph.D. requirements of the TU Delft, where the candidate will be enrolled for Ph.D. studies.
The applicant must also apply for the TIRAMISU (DC2.4) position using the following link: https://tiramisu-project.eu/vacancies/application-procedure