Lead Custom Layout Design Engineer

11 Minutes ago • 4 Years +
Software Development & Engineering

Job Description

This role involves custom layout design, focusing on floorplanning, matching guides, resistor/capacitor placement, and noise reduction. The engineer will handle top-level hierarchy floorplans for blocks and power, and work with high-speed mixed-signal PHYs like SerDes, USB, and DDR. Collaboration with the analog circuit design team is crucial to ensure high efficiency and quality in analog layout design.
Good To Have:
  • Work experience in PERC run
  • Work experience in FinFET layout
  • Work experience in ESD/Latch-up
  • Work experience in cooperation with digital P&R team
Must Have:
  • BSEE degree with 4+ years of applicable experience in analog/custom layout of advanced technology nodes
  • Proficient with Layout edit/verify tools, like Virtuoso XL, Pegasus/Calibre DRC/LVS
  • Proficient with EMIR tools, like Voltus-FI
  • Hands-on experience conducting DRC/LVS/ERC analysis, EMIR analysis, and recommending appropriate solutions
  • Fundamental understanding of IC design technology and process/methodology

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Position Description:

  • Responsible for custom layout floorplan, matching guides, resistor/capacitor placement, reduce coupling & noise, sensitive signals routing, mix-signals routing, etc.
  • Responsible for custom layout top level hierarchy floorplan for blocks/powers
  • Responsible for high-speed mixed-signal PHY such as SerDes, USB, DDR, etc
  • Responsible for cooperation with analog circuit design team to ensure high efficiency and quality for analog layout design.

Position Requirements:

  • BSEE degree with 4+ years of applicable experience in analog/custom layout of advanced technology nodes
  • Proficient with Layout edit/verify tools, like Virtuoso XL, Pegasus/Calibre DRC/LVS, etc.
  • Proficient with EMIR tools, like Voltus-FI
  • Hands-on experience conducting DRC/LVS/ERC analysis, EMIR analysis, and recommending appropriate solutions
  • Fundamental understanding of IC design technology and process/methodology
  • Essential that the individual demonstrates good teamwork and self-motivation
  • Good communication skills in English
  • Work experience in PERC run is a plus
  • Work experience in FinFET layout is a plus
  • Work experience in ESD/Latch-up is a plus
  • Work experience in cooperation with digital P&R team is a plus

We’re doing work that matters. Help us solve what others can’t.

About Us

Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.

Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

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