Lead Custom Layout Design Engineer

Cadence is seeking a Lead Custom Layout Design Engineer responsible for custom layout floorplan, matching guides, resistor/capacitor placement, and sensitive signal routing. The role involves working with high-speed mixed-signal PHYs like SerDes, USB, and DDR, and collaborating with analog circuit design teams. Candidates should have a BSEE degree with 4+ years of experience in analog/custom layout using advanced technology nodes, proficiency with tools like Virtuoso XL and Calibre, and experience in DRC/LVS/ERC and EMIR analysis.

Must Have

• Responsible for custom layout floorplan, matching guides, resistor/capacitor placement, reduce coupling & noise, sensitive signals routing, mix-signals routing
• Responsible for custom layout top level hierarchy floorplan for blocks/powers
• Responsible for high-speed mixed-signal PHY such as SerDes, USB, DDR
• Responsible for cooperation with analog circuit design team to ensure high efficiency and quality for analog layout design
• BSEE degree with 4+ years of applicable experience in analog/custom layout of advanced technology nodes
• Proficient with Layout edit/verify tools, like Virtuoso XL, Pegasus/Calibre DRC/LVS
• Proficient with EMIR tools, like Voltus-FI
• Hands-on experience conducting DRC/LVS/ERC analysis, EMIR analysis, and recommending appropriate solutions
• Fundamental understanding of IC design technology and process/methodology
• Demonstrates good teamwork and self-motivation
• Good communication skills in English

Good to Have

• Work experience in PERC run
• Work experience in FinFET layout
• Work experience in ESD/Latch-up
• Work experience in cooperation with digital P&R team

Position Description:

• Responsible for custom layout floorplan, matching guides, resistor/capacitor placement, reduce coupling & noise, sensitive signals routing, mix-signals routing, etc.
• Responsible for custom layout top level hierarchy floorplan for blocks/powers
• Responsible for high-speed mixed-signal PHY such as SerDes, USB, DDR, etc
• Responsible for cooperation with analog circuit design team to ensure high efficiency and quality for analog layout design.

Position Requirements:

• BSEE degree with 4+ years of applicable experience in analog/custom layout of advanced technology nodes
• Proficient with Layout edit/verify tools, like Virtuoso XL, Pegasus/Calibre DRC/LVS, etc.
• Proficient with EMIR tools, like Voltus-FI
• Hands-on experience conducting DRC/LVS/ERC analysis, EMIR analysis, and recommending appropriate solutions
• Fundamental understanding of IC design technology and process/methodology
• Essential that the individual demonstrates good teamwork and self-motivation
• Good communication skills in English
• Work experience in PERC run is a plus
• Work experience in FinFET layout is a plus
• Work experience in ESD/Latch-up is a plus
• Work experience in cooperation with digital P&R team is a plus