Lead Layout Engineer

4 Months ago • 2-7 Years
Software Development & Engineering

Job Description

This Lead Layout Engineer role involves developing layouts and floorplans, conducting analyses, and collaborating with stakeholders. Responsibilities include creating accurate designs, troubleshooting issues, and staying updated on verification methods. The role requires experience in layout design and verification tools, automation, and communication skills. The job overview highlights the need for experience in Finfet & GAA technologies, knowledge of scripting languages, and understanding of back-end views.
Good To Have:
  • Understanding of stdcell architecture, physical verification like DRC, LVS, ERC.
  • Knowledge of scripting language is mandatory (Proficient in PERL/Python & SHELL scripting) TCL, and Svrf Scripting is needed.
  • Understanding of different Back end views and their Formats and usage at downstream SOCs.
Must Have:
  • Experience in Finfet technology, layout design, and DRC limitations.
  • Strong automation skills with Perl/Python, skill, SVRF & tcl.
  • Proficient in physical verification flow & debug, like DRC, LVS, ERC.
  • Proficient in Cadence Virtuoso layout editor and Calibre physical verification flow.
  • Good Programming skills and hands on experience in Perl, Python , shell and tcl languages.

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Company:

Qualcomm India Private Limited

Job Area:

Engineering Services Group, Engineering Services Group > Layout Engineer

General Summary:

Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues.

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 3+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.
OR
Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 5+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.
OR
High School diploma or equivalent and 7+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.

• 3+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap).

Job Overview:

2-5 years of experience in Std cell and Custom layout design with hands on expertise in latest Finfet & GAA technologies 7nm, 5nm, 3nm, 2nm

Good understanding of stdcell architecture, physical verification like DRC, LVS, ERC.

Good knowledge in optimized layout design for better Area & Performance.

Knowledge of scripting language is mandatory (Proficient in PERL/Python & SHELL scripting) TCL, and Svrf Scripting is needed.

Good Programming skills and hands on experience in Perl, Python , shell and tcl languages.

Understanding of different Back end views and their Formats and usage at downstream SOCs.

SVRF coding of rule decks and or modifying existing rules/SVRF for manipulating layout views.

 

Required Qualification:

Sound knowledge & hands on experience in Finfet technology, layout design and DRC limitations.

Strong Automation skills with multiple languages like Perl/Python, skill, SVRF& tcl

Cross Domain work with Automation spanning multiple domains like circuit design, Layout and char teams.

Excellent communication skills and ability to work across multiple projects is critical

 

 

Minimum Qualification:

Proficient in physical verification flow & debug, like DRC, LVS, ERC, Boundary conditions.

Proficient in Cadence Virtuoso layout editor and Calibre physical verification flow.

2-6 years of experience in the area of Automation and Back End Layouts is required.

Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.

If you would like more information about this role, please contact Qualcomm Careers.

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