Lead Layout Engineer

Company:

Qualcomm India Private Limited

Job Area:

Engineering Services Group, Engineering Services Group > Layout Engineer

General Summary:

Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues.

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 3+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.
OR
Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 5+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.
OR
High School diploma or equivalent and 7+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.

• 3+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap).

Job Overview:

2-5 years of experience in Std cell and Custom layout design with hands on expertise in latest Finfet & GAA technologies 7nm, 5nm, 3nm, 2nm

Good understanding of stdcell architecture, physical verification like DRC, LVS, ERC.

Good knowledge in optimized layout design for better Area & Performance.

Knowledge of scripting language is mandatory (Proficient in PERL/Python & SHELL scripting) TCL, and Svrf Scripting is needed.

Good Programming skills and hands on experience in Perl, Python , shell and tcl languages.

Understanding of different Back end views and their Formats and usage at downstream SOCs.

SVRF coding of rule decks and or modifying existing rules/SVRF for manipulating layout views.

 

Required Qualification:

Sound knowledge & hands on experience in Finfet technology, layout design and DRC limitations.

Strong Automation skills with multiple languages like Perl/Python, skill, SVRF& tcl

Cross Domain work with Automation spanning multiple domains like circuit design, Layout and char teams.

Excellent communication skills and ability to work across multiple projects is critical

 

 

Minimum Qualification:

Proficient in physical verification flow & debug, like DRC, LVS, ERC, Boundary conditions.

Proficient in Cadence Virtuoso layout editor and Calibre physical verification flow.

2-6 years of experience in the area of Automation and Back End Layouts is required.

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