ASIC RTL Design Engineer(Camera) - Sr Lead

This role involves designing and developing next-generation SoC subsystems for mobile phone cameras, focusing on ASIC development using the latest technology nodes. The candidate will cover all aspects of the VLSI development cycle, including architecture, micro-architecture, synthesis, PD interaction, and design convergence. Responsibilities include digital design and RTL development, implementing designs with Verilog/SV, integrating complex subsystems, and collaborating with various engineering teams. The role also requires analyzing reports and utilizing tools like Spyglass, 0-in, DC-Compiler, Prime time, synthesis, and simulation.

Must Have

• Design and develop next-generation SoC camera subsystems.
• Work on ASIC development using latest technology nodes.
• Understand VLSI development cycle: architecture, micro-architecture, synthesis, PD, design convergence.
• Solid experience in digital front-end design for ASICs.
• Expertise in RTL micro-architecture and Verilog/SV coding for complex designs.
• Proficiency with bus protocols: AHB, AXI, and NOC designs.
• Experience in low-power design methodology and clock domain crossing.
• Understand full RTL to GDS flow, interact with DFT and PD teams.
• Experience with Spyglass Lint/CDC checks and waiver creation.
• Formal verification experience using Cadence LEC.
• Ability to create unit-level test plans.
• Perform digital design and RTL development.
• Integrate and deliver complex subsystems to SoC.
• Collaborate with Systems, Verification, SoC, SW, PD, and DFT teams.
• Analyze reports and use tools like Spyglass, DC-Compiler, Prime time.

Good to Have

• Experience in mobile Multimedia/Camera design
• DSP /ISP knowledge
• Working knowledge of timing closure
• Expertise in Perl, TCL language
• Expertise in post-Si debug

Perks & Benefits

• Health: Qualcomm offers a world-class health benefit option providing world-class coverage to employees and their eligible dependents.
• Wealth: Our programs are designed to help employees build and prepare for a financially secure future.
• Self: Our self and family resources help you build emotional/mental strength and resilience, as well as define your purpose — in life and at work.
• Wellbeing: Qualcomm’s wellbeing programs and resources offer support to help employees Live+Well and Work+Well, so they can unlock their full potential at home, at work, and everywhere between.

Job Description

General Summary:

Job Function : Camera Design Lead/Staff

Candidate will be responsible for design/developing next generation SoCs sub systems for mobile phone camera . Candidate will be working on ASIC based on the latest technology nodes. This role will require the candidate to understand and work on all aspects of VLSI development cycle like architecture, micro architecture, Synthesis/PD interaction and design convergence.

Skills/Experience

5-10 years with Masters (6 to 10 years with Bachelors)

Solid experience in digital front end design for ASICs

Solid Expertise in RTL microarchitecture and design coding in Verilog/SV for complex designs with multiple clock and power domains

Expertise with various bus protocols like AHB, AXI and NOC designs

Experience in low power design methodology and clock domain crossing designs

Understanding of full RTL to GDS flow to interact with DFT and PD teams

Experience in Tools like Spyglass Lint/CDC checks and waiver creation

Experience in formal verification with Cadence LEC

Experience in mobile Multimedia/Camera design is a plus

DSP /ISP knowledge is a plus.

Working knowledge of timing closure is a plus

Expertise in Perl, TCL language is a plus

Expertise in post-Si debug is a plus

Good documentation skills

Ability to create unit level test plan

General

Should possess good communication skills to ensure effective interaction with Engineering Management and mentor group members.

Should be self-motivated and good team working attitude and need to function with little direct guidance or supervision

Responsibilities

Digital design and development (RTL) working in close collaboration with Multi-site leads

Developing the micro architecture and implementing the design using Verilog/SV. Integrate and deliver complex subsystem to SoC

Design and implement defined tasks independently.

Work in close coordination with Systems, Verification, SoC team , SW team, PD & DFT teams to get the goals completed.

Analyze reports/waivers or run various tools : Spyglass, 0-in, DC-Compiler, Prime time, synthesis, simulation etc

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

OR

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.

OR

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.