NPU STA/Timing Engineer

17 Hours ago • 5-10 Years

Network Engineering

Job Description

As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. You will collaborate with cross-functional teams to develop solutions and meet performance requirements. This role specifically focuses on STA setup, timing analysis, validation, and debug for multi-mode, multi-voltage domain designs, utilizing tools like Primetime and Tempus, and developing automation scripts.

Good To Have:

In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling.
Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus).
Knowledge of Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation.
Proficient in scripting languages – TCL, Perl, Awk.
Basic knowledge of device physics.

Must Have:

STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs.
Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus.
Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.
Experience in design automation using TCL/Perl/Python.
Familiar with digital flow design implementation RTL to GDS: ICC, Innovous, PT/Tempus.
Familiar with process technology enablement: Circuit simulations using Hspice/FineSim, Monte Carlo.
Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints.
Hands-on experience with STA tools - Prime-time, Tempus.
Experience in driving timing convergence at Chip-level and Hard-Macro level.

Perks:

Health: Qualcomm offers a world-class health benefit option providing world-class coverage to employees and their eligible dependents.
Wealth: Our programs are designed to help employees build and prepare for a financially secure future.
Self: Our self and family resources help you build emotional/mental strength and resilience, as well as define your purpose — in life and at work.
Wellbeing: Qualcomm’s wellbeing programs and resources offer support to help employees Live+Well and Work+Well, so they can unlock their full potential at home, at work, and everywhere between.

Add these skills to join the top 1% applicants for this job

cross-functional

communication

unity

game-texts

fpga

back-end

python

perl

Job Posting Date

2025-10-15

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications:

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Responsibilities:

STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs.
Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus.
Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.
Evaluate multiple timing methodologies/tools on different designs and technology nodes.
Work on automation scripts within STA/PD tools for methodology development.
Good Technical writing and Communication skills, should be willing to work in cross-collaborative environment
Experience in design automation using TCL/Perl/Python.
Familiar with digital flow design implementation RTL to GDS : ICC, Innovous , PT/Tempus
Familiar with process technology enablement: Circuit simulations using Hspice/FineSim, Monte Carlo.

Education : B.Tech or MTech/MS in Electrical/Electronics/Microelectronics/VLSI.

Preferred Qualification/Skills

5 - 10 years of experience in STA/Timing
Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling
Hands-on experience with STA tools - Prime-time, Tempus
Have experience in driving timing convergence at Chip-level and Hard-Macro level
In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling,
Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus)
Knowledge of Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation.
Proficient is scripting languages – TCL, Perl, Awk
Basic knowledge of device physics