Physical Design Engineer

We are seeking a skilled Physical Design Engineer to perform the implementation of Neural Processing Units (NPU) designs from RTL to GDSII. This role involves creating a manufacturing-ready design database and executing the full physical design flow, including synthesis, floorplanning, place and route, clock tree synthesis, routing, static timing analysis, power and clock distribution, reliability and noise analysis. The engineer will also perform verification and signoff tasks and optimize designs for power, performance, and area (PPA).

Must Have

• Perform implementation of Neural Processing Units (NPU) designs from RTL to GDSII.
• Execute all stages of the physical design flow (Synthesis, Floorplanning, P&R, CTS, Routing, STA, Power/clock distribution, Reliability/noise analysis).
• Perform verification and signoff tasks (Formal equivalence, Power integrity, Layout verification, ERC).
• Analyze design results and recommend fixes for violations.
• Optimize designs for power, performance, and area (PPA).
• Knowledge of low power design techniques.
• Experience with physical/structural design flow.
• Proficiency with timing constraints, timing closure, and physical clock design.
• Proficiency with industry-standard EDA tools.
• Bachelor’s (NFQ 8) or Master’s (NFQ 9) degree in Engineering or equivalent.

Job Description

We are seeking a skilled Physical Design Engineer to perform the implementation of Neural Processing Units (NPU) designs from RTL to GDSII. This role involves creating a manufacturing-ready design database and executing the full physical design flow.

Key Responsibilities

• Execute all stages of the physical design flow, including:
• Synthesis
• Floorplanning
• Place and Route (P&R)
• Clock Tree Synthesis (CTS)
• Routing
• Static Timing Analysis (STA)
• Power and clock distribution
• Reliability and noise analysis
• Perform verification and signoff tasks such as:
• Formal equivalence verification
• Static and dynamic power integrity checks
• Layout verification
• Electrical Rule Checking (ERC)
• Analyze design results and recommend fixes for violations to support current and future product architectures.
• Optimize designs for power, performance, and area (PPA).
• Contribute to the development and automation of physical design methodologies and flows.

Required Skills & Experience

• Low power design techniques
• Physical/structural design flow
• Timing constraints
• Timing closure and physical clock design
• Proficiency with industry-standard EDA tools

Qualifications:

• Bachelor’s (NFQ 8) or Master’s( NFQ 9)degree in Engineering or equivalent