Physical Design Engineer

We are looking for VLSI Physical Design Engineers to work on NVIDIA GPU and Mobile chips in Hsinchu, Taiwan. This senior role involves full chip floorplanning, power/clock distribution, timing optimization, place & route, timing closure, power/signal integrity analysis, and physical verification. Candidates should have a BS in Engineering or Science, be proficient with EDA tools from Synopsys, Cadence, or Ansys, and possess 2+ years of experience in these areas. Collaboration with RTL, DFT, and Circuit designers is essential.

Must Have

• A senior role in physical design for NVIDIA GPU and Mobile chips
• Participate in various aspects of physical design, including full chip floorplanning, power/clock distribution, timing optimization, place & route, timing closure, power/signal integrity analysis, and physical verification
• Troubleshoot a wide variety of design and flow complicated issues, and apply proactive intervention
• Collaborate with RTL, DFT and Circuit designers to ensure high quality of design implementation
• BS in Engineering or Science or equivalent experience
• Power user of EDA tools from Synopsys (ICC2/DC/PT/STAR-RC), Cadence (EDI/Innovus/Voltus) or Ansys (Redhawk)
• Experience in Clock/Power Distribution, P&R, Timing closure, RC Extraction, and verification on advanced technology nodes
• 2+ years of experience in physical design areas

Good to Have

• MS in Engineering or Science
• Knowledge in FinFET technology, circuit design, and package design
• Experience in physical verification tools from Synopsys (ICV) or Mentor (Calibre)
• Proficiency in Perl, Python, TCL and Makefile scripts

Job Description

Company

Job Requisition ID

JR2008499

Job Category

Engineering

Time Type

Full time

We are now looking for VLSI Physical Design Engineers in Hsinchu office, Taiwan. We utilize latest process technology, advanced EDA tools, and sophisticated design methodology. We always work on the most challenging designs, and push for performance limit.

What you’ll be doing:

• A senior role in physical design for NVIDIA GPU and Mobile chips.
• Participate in various aspects of physical design, including full chip floorplanning, power/clock distribution, timing optimization, place & route, timing closure, power/signal integrity analysis, and physical verification. Troubleshoot a wide variety of design and flow complicated issues, and apply proactive intervention.
• Collaborate with RTL, DFT and Circuit designers to ensure high quality of design implementation.

What we need to see:

• BS in Engineering or Science or equivalent experience.
• Power user of EDA tools from Synopsys (ICC2/DC/PT/STAR-RC), Cadence (EDI/Innovus/Voltus) or Ansys (Redhawk).
• Experience in Clock/Power Distribution, P&R, Timing closure, RC Extraction, and verification on advanced technology nodes.
• 2+ years of experience in above areas.

Ways to stand out from the crowd:

• MS in Engineering or Science.
• Knowledge in FinFET technology, circuit design, and package design.
• Experience in physical verification tools from Synopsys (ICV) or Mentor (Calibre).
• Proficiency in Perl, Python, TCL and Makefile scripts.