Physical Design Engineer

Qualcomm Technologies, Inc. is seeking Physical Design Engineers for its Digital ASIC Team. This role involves innovating, developing, and implementing chips and cores using advanced tools and technologies. Responsibilities include the complete Physical Design Flow and deliveries of complex, high-speed, low-power designs such as GPU, Camera, DDR, Modem, and Audio. Tasks also cover the development and enablement of low-power implementation methods, customized P&R to achieve area reduction, performance, and power goals, and understanding functional and test constraints for place and route, timing optimization, and verification.

Must Have

• Innovate, develop, and implement chips and cores using state-of-the-art tools and technologies.
• Be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power designs.
• Develop and enable low power implementation methods.
• Perform customized P&R to achieve area reduction, performance, and power goals.
• Understand functional and test (DFT) mode constraints for place and route.
• Perform floorplanning, power planning, IR drop analysis, cell placement.
• Execute multi-mode & multi-corner (MMMC) clock tree synthesis, routing.
• Conduct timing optimization and closure, RC extraction, signal integrity, cross talk noise and delay analysis.
• Debug timing violations for MMMC designs, implement timing fixes and functional ECOs.
• Debug and fix physical violations, and perform formal verification.
• Possess deep knowledge on scripting and software languages including Python, PERL/TCL, Linux/Unix shell and C.
• Design, verify, and deliver complex Physical Design solutions from netlist and timing constraints to the final product.
• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience OR PhD in Science, Engineering, or related field.

Good to Have

• 6+ years industry experience in Physical Design.
• Place & Route tool experience on Cadence Innovus and/or Synopsys Fusion Compiler.
• Timing closure experience in Synopsys PTSI.
• Formal verification experience.
• Power domain analysis experience.
• Physical verification experience.

Perks & Benefits

• World-class health benefit option providing world-class coverage to employees and their eligible dependents.
• Programs designed to help employees build and prepare for a financially secure future.
• Self and family resources to build emotional/mental strength and resilience, and define purpose.
• Wellbeing programs and resources to support employees to Live+Well and Work+Well.

Job Posting Date

2025-11-17

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Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.

QCTs Digital ASIC Team is actively seeking candidates for several physical design engineering positions in our SOC and core design team. As a physical design engineer you will innovate, develop, and implement chips and cores using state-of-the-art tools and technologies.

You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power designs such as GPU, Camera and other MM, DDR, Modem, Audio . Tasks also involve the development and enablement of low power implementation methods, customized P&R to achieve area reduction, performance, and power goals. Additional responsibilities in this role involves good understanding of functional and test (DFT) mode constraints for place and route, floorplanning, power planning, IR drop analysis, cell placement, multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization and closure, RC extraction, signal integrity, cross talk noise and delay analysis, debugging timing violations for MMMC designs, implementing timing fixes and functional ECOs, debugging and fixing physical violations, and formal verification. The individual also should have deep knowledge on scripting and software languages including Python, PERL/TCL, Linux/Unix shell and C. This individual will design, verify, and deliver complex Physical Design solutions from netlist and timing constraints to the final product.

Preferred Qualifications

6+ years industry experience in the following areas:

• Physical Design
• Place & Route tool experience on Cadence Innovus and/or Synopsys Fusion Compiler
• Timing closure experience in Synopsys PTSI
• Formal verification experience
• Power domain analysis experience
• Physical verification experience

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

OR

Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.

OR

PhD in Science, Engineering, or related field.

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com

or call Qualcomm's toll-free number found here

. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

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EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

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Pay range and Other Compensation & Benefits:

$115,600.00 - $173,400.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm.  We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus).  In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link

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If you would like more information about this role, please contact Qualcomm Careers

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