Physical Design - engineer

Qualcomm India Private Limited is seeking a Physical Design Engineer to perform physical implementation activities for sub-systems, including floor-planning, place and route, CTS, formal and physical verification, PDN, timing closure, and power optimization. The role requires expertise in PPA critical cores, high-frequency data-path timing convergence, and proficiency with tools like Synopsys ICC2/Cadence Innovus. Collaboration with design, DFT, and PNR teams is essential, along with strong Tcl/Perl scripting skills.

Must Have

• Perform Physical Implementation activities (Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure, power optimization).
• Good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions.
• Knowledge in timing convergence of high frequency data-path intensive Cores and advanced STA concepts.
• Knowledge in Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus.
• Good understanding of clocking architecture.
• Ability to work in close collaboration with design, DFT and PNR teams.
• Good knowledge of Tcl/Perl Scripting.
• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field with 2+ years of Hardware Engineering or related work experience, OR Master's with 1+ year, OR PhD.
• 1-3 years of experience in Physical Design/Implementation.

Perks & Benefits

• World-class health benefit options.
• Programs to help build a financially secure future.
• Self and family resources for emotional/mental strength and resilience.
• Wellbeing programs and resources for Live+Well and Work+Well.
• Continuous learning and development programs.
• Tuition reimbursement.
• Mentorships.

Job Posting Date

2025-10-10

General Summary:

• Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization.
• Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions.
• Knowledge in timing convergence of high frequency data-path intensive Cores and advanced STA concepts
• Knowledge in Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus
• Good understanding of clocking architecture.
• Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc.
• Good knowledge of Tcl/Perl Scripting
• Strong problem-solving skills and good communication skills.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

OR

• Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

OR

• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

1-3 yrs years of experience in Physical Design/Implementation