Principal Design Engineer
About the job
SummaryBy Outscal
Cadence seeks a Principal Design Engineer with deep knowledge of high-speed Serdes/Memory interfaces (PCIe Gen3/4/5, GDDRx/DDRx/LPDDRx) and strong Analog/I/O design fundamentals. Experience in leading and mentoring junior engineers is essential. Prior experience on cutting-edge technology nodes (16nm/10nm/12nm/7nm) is a plus.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Education: BE/ B Tech/ ME/ M Tech / MS
- In-depth understanding of high-speed Serdes/Memory interface circuits like I/O’s,PLL’s, Clocking, Datapaths.
- Hands on experience on PCIe Gen3/4/5, GDDRx/DDRx/LPDDRx Serdes and memory interface circuits.
- Strong Analog Design and I/O Design fundamentals. Knowledge of ESD/Reliability/SI/PI.
- Experience in leading and mentoring Junior Engineers.
- Must have excellent written and verbal communication skills as well as good problem-solving skills.
- Prior experience of working on cutting edge technology nodes like 16nm/10nm/12nm/7nm is added advantage.
We’re doing work that matters. Help us solve what others can’t.
About The Company
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