Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.
The Cadence Advantage
Requirement:
Will be responsible for Physical Design tasks at subsystem, sub-chip, and/or full-chip level. The tasks will include Synthesis, Floorplanning, Power planning, Placement, CTS and custom clocking, Routing, Static Timing analysis, Physical Verification, Formal Equivalency, IREM analysis. Expertise in FullChip tasks is added advantage. Should have leadership skills , leading team , handling flat projects.
Expertise in: Physical design flow from RTL to GDSII
Mandatory skills: Proficiency in TCL, Perl scripting
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