Principal Design Engineer

1 Year ago • 5-10 Years • Software Development & Engineering • $146,850 PA - $220,000 PA

Job Summary

Job Description

Marvell is seeking a Principal Design Engineer to join their Data Center Engineering business group. This role involves leading micro-architecture and RTL development, as well as HW/SW co-design efforts for high-performance mixed-signal ICs used in high-speed interconnects for hyperscaler data centers. Responsibilities include designing DSP logic, collaborating with architects and verification engineers, and ensuring the delivery of complex, timing-critical designs through front-end flows, including timing closure and power optimization. The candidate will work on the company's connectivity product roadmap, contributing to innovative technology that fuels communication in AI clusters.
Must have:
  • Bachelor's degree in CS/EE or related field and 10+ years of experience OR Master's/PhD and 5+ years of experience
  • Strong understanding of Digital Signal Processing, Forward Error Correction codes, and physical layer protocols
  • Extensive experience in Verilog/SystemVerilog, Synthesis, STA, low power design, Spyglass, and RTL quality checks
  • Hands-on experience in scripting languages like Perl/Python
  • Proven track record of delivering production-quality designs
Good to have:
  • Domain expertise in 802.3 standards and Serdes design
Perks:
  • Bonus and equity
  • Flexible time off
  • 401k
  • Year-end shutdown
  • Floating holidays
  • Paid time off to volunteer

Job Details

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

In this role you’ll be a member of the Data Center Engineering business group. Our group owns the digital design of high performance mixed signal ICs used in high speed interconnects in hyperscaler data centers. These chips implement advanced digital signal processing algorithms and protocol processing to meet demanding performance, speed, power and latency requirements of the interconnects that power the communication in AI clusters.

What You Can Expect

As a Principal Design Engineer, you will lead micro-architecture and RTL development and HW/SW co-design efforts working across multi-functional teams, in developing state-of-the-art designs for the up and coming connectivity product roadmap.

Additional responsibilities will include, but not be limited to:
• Responsible for micro-architecture design and development of DSP logic.
• Working with Architects and Verification engineers to deliver develop complex, high performance and timing critical designs through all aspects of the front-end design flow (incl. timing closure and power optimization)

What We're Looking For

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 10+ years of related professional experience.
• Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5+ years of experience.
• Strong understanding of Digital Signal Processing, Forward Error Correction codes and physical layer protocols through hands on prior experience.
• Extensive experience in Verilog/SystemVerilog, Synthesis, STA, low power design, Spyglass and Quality checks of the implemented RTL for LINT, CDC.
• Hands on experience in scripting language such as Perl/Python.
• Proven track record of delivering production-quality designs on aggressive development schedules.
• Domain expertise in 802.3 standards and Serdes design is a plus.

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements 

At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

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About The Company

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

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