The Wireless SoC Radio Team is seeking an RFIC Layout Engineer to design state-of-the-art, energy-efficient CMOS radios. Responsibilities include designing RF, analog, and mixed-signal blocks, working with FinFet technologies, and layout design for complex SoC products. This role impacts Apple's advanced radios in millions of products. You will work closely with the RFIC design team, focusing on layout and verification of custom RF and analog IP. The position requires a strong understanding of layout techniques, parasitic minimization, RF shielding, high-frequency routing, and advanced process effects. You will interpret CALIBRE DRC, ERC, LVS, use CADENCE tools, and potentially lead layout engineers for top-level integration. The ability to identify failure-prone circuit and layout structures and collaborate with designers is crucial. Scripting skills in PERL or SKILL are also beneficial.
Good To Have:- Capability to lead other layout engineers for top-level integration
- Proactively work with circuit designers for problem resolution
Must Have:- BS and 3+ years of relevant industry experience
- FinFet experience
- Custom RF/analog layout for radio transceivers
- Deep sub-micron CMOS knowledge
- Layout techniques for device matching, parasitics, RF shielding, high frequency routing
- Solid understanding of RC delay, electromigration, and coupling
- Understanding of guard rings, DNW, PN junctions, LOD, WPE
- Proficiency in interpreting CALIBRE DRC, ERC, LVS
- Knowledge of CADENCE layout tools
- Excellent communication and cross-functional teamwork skills
- Ability to recognize failure prone circuit and layout structures
- Scripting skills in PERL or SKILL
Perks:- Discretionary employee stock programs
- Discretionary restricted stock unit awards
- Discounted Apple stock purchase
- Comprehensive medical and dental coverage
- Retirement benefits
- Discounted products
- Free services
- Reimbursement for certain educational expenses