The Wireless SoC Radio Team is seeking an RFIC Layout Engineer to design state-of-the-art, energy-efficient CMOS radios. Responsibilities include designing RF, analog, and mixed-signal blocks, working with FinFet technologies, and layout design for complex SoC products. This role impacts Apple's advanced radios in millions of products. You will work closely with the RFIC design team, focusing on layout and verification of custom RF and analog IP. The position requires a strong understanding of layout techniques, parasitic minimization, RF shielding, high-frequency routing, and advanced process effects. You will interpret CALIBRE DRC, ERC, LVS, use CADENCE tools, and potentially lead layout engineers for top-level integration. The ability to identify failure-prone circuit and layout structures and collaborate with designers is crucial. Scripting skills in PERL or SKILL are also beneficial.