Senior Layout Designer

Designs, implements, and verifies the layout design of test structures and circuits which enable the development of Intel's leading-edge silicon technologies. These test structures are tailored to model Quality and Reliability (QnR) parameters essential for technology qualification. The role involves collaboration with Technology Development (TD), Design Technology Platform (DTP), and QnR engineers to define and execute requirements for new Test Chips.

Must Have

• Develop custom layout design of analog blocks, complex digital, mixed signal blocks, standard cell libraries, or memory compilers.
• Perform detailed physical array planning, area optimization, digital block synthesis, critical wire analysis, custom leaf, cell layout, and compiler assembly coding.
• Conduct complete layout verification including design rule compliance, SoC integration specs, electron migration, voltage drop (IR), selfheat, ESD, and other reliability checks.
• Use custom auto-routers and custom placers to efficiently construct layout.
• Provide feedback to circuit design engineers for new feature feasibility studies and implement circuit enhancement requests.
• Develop and drive new and innovative layout methods to improve productivity and quality.
• Troubleshoot a wide variety of issues up to and including design and tool/flow/methodology issues used for layout design.

Good to Have

• Experience in CMOS VLSI design concepts, flows, and EDA tools.
• Programming/scripting in C/C++, Python.
• Experience with UNIX/Linux operating systems.
• Experience in layout design, Cadence Virtuoso Layout Suite, layout debug (DRC, LVS).
• Experience in EDA Tools, Flows, and Methodology (TFM) development.
• Experience with Cadence SKILL programming languages.
• Experience leading and coordinating small/medium size group of layout designers.
• Strong initiative, analytical/problem solving skills, communication skills, team working skills, ability to multitask.
• Design, implement, verify, and support the enablement and adoption of hardware design tools, flows, and methodologies.
• Define methodologies for hardware development related to technology node and EDA tool enabling.
• Create and verify unique hardware designs, assemble design platforms, and integrate components into hierarchical systems.
• Develop, test, and analyze engineering design automation tools, flow, and methodologies to improve efficiency and optimize power and performance.
• Support development and enhancement of platforms, databases, scripts, and tools flows for design automation.
• Build deep understanding of digital design, verification, structural and physical layout, full-chip integration, power, and performance clocking, and/or timing.
• Collaborate with EDA vendors on defining and early testing of next-generation design tools.

Perks & Benefits

• Competitive pay
• Stock options
• Bonuses
• Health benefits
• Retirement benefits
• Vacation

Job Description:

Designs, implements, and verifies the layout design of test structures and circuits which enable the development of Intel's leading-edge silicon technologies. The test structures are tailored to model Quality and Reliability (QnR) parameters which are essential to the qualification life cycle for each technology.

You will have the opportunity to work with partners in Technology Development (TD), Design Technology Platform (DTP), and a world class team of QnR engineers to understand, define, and execute the requirements of new trailblazing Test Chips.

Primary responsibilities include but are not limited to:

• Develops custom layout design of analog blocks, complex digital, mixed signal blocks, standard cell libraries, or memory compilers (e.g., bitcells, SRAMs, Register Files).
• Performs detailed physical array planning, area optimization, digital block synthesis, critical wire analysis, custom leaf, cell layout, and compiler assembly coding.
• Conducts complete layout verification including design rule compliance, SoC integration specs, electron migration, voltage drop (IR), selfheat, ESD, and other reliability checks. Uses custom auto-routers and custom placers to efficiently construct layout.
• Provides feedback to circuit design engineers for new feature feasibility studies and implements circuit enhancement requests.
• Develops and drives new and innovative layout methods to improve productivity and quality.
• Troubleshoots a wide variety of issues up to and including design and tool/flow/methodology issues used for layout design.

Additional responsibilities:

• Designs, implements, verifies, and supports the enablement and adoption of hardware design tools, flows, and methodologies.
• Defines methodologies for hardware development related to technology node and EDA tool enabling.
• Creates and verifies unique hardware designs, assembles design platforms, and integrates components into hierarchical systems to provide deployment coverage for end-to-end EDA tool testing on new technology nodes.
• Develops, tests, and analyzes engineering design automation tools, flow, and methodologies to improve efficiency and optimize power and performance.
• Supports development and enhancement of platforms, databases, scripts, and tools flows for design automation.
• Builds deep understanding of digital design, verification, structural and physical layout, full-chip integration, power, and performance clocking, and/or timing to enhance future TFM development.
• Collaborates with EDA vendors on defining and early testing of next-generation design tools.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Knowledge and/or experience listed below would be obtained through a combination of your school, work and/or classes and/or research and/or relevant previous job and/or internship experiences.

Minimum Qualifications:

• Bachelor's degree in Electrical/Computer Engineering or related field and 6+ years of experience OR a Master's degree in Electrical/Computer Engineering or related field and 4+ years of experience OR a PhD in Electrical/Computer Engineering or related field and 2+ years of experience in:
• Layout design & Cadence Virtuoso

Preferred qualifications:

• 6+ years of experience in:
• CMOS VLSI design concepts, flows, and EDA tools
• Programming/scripting in C/C++, Python.
• UNIX/Linux operating systems.
• 8+ years of experience in layout design, Cadence Virtuoso Layout Suite, layout debug (DRC, LVS).
• 4+ years of experience in EDA Tools, Flows, and Methodology (TFM) development
• 1+ year of experience with Cadence SKILL programming languages.
• Experience leading and coordinating small/medium size group of layout designers.
• Strong initiative, analytical/problem solving skills, communication skills, team working skills, ability to multitask and be able to work with a diverse team located in different geos.

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, Oregon, Hillsboro

Additional Locations:

US, Arizona, Phoenix

Business group:

Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003

Annual Salary Range for jobs which could be performed in the US: 121,050.00 USD - 227,620.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.