Senior Member of Technical Staff #91498

5 Minutes ago • 7 Years + • $212,360 PA - $215,000 PA

Software Development & Engineering

Job Description

Rivos is seeking a Senior Member of Technical Staff to specialize in SOC clock implementation and lead a team of clock design engineers. This role involves defining clock methodology for System on Chip, including structure, simulation, and physical implementation for high-performance, low-power CPU clusters and memory modules. The engineer will develop efficient clock structures, analyze clock tree quality, and collaborate with the SOC physical design team. Key responsibilities also include working with various design tools and addressing CMOS circuit challenges like low power, EM, IR, noise, and DFM.

Must Have:

Master’s or foreign equivalent in Electrical Engineering or related field.
7 years of experience in job offered or related occupation.
1 year of prior work experience in Clock Planning, Design, Execution, Clock timing, Clock FEV, Clock quality signoff and Power reduction.
1 year of prior work experience in designing and developing workflow methodology to ensure seamless integration of design through multiple hierarchies.
1 year of prior work experience in designing clocks ranging from 200MHz to 3GHz High-speed clocks for Cache modules/Memory Sub-systems/DDR/Fabrics and Display with ultra-low skews without sacrificing power.
1 year of prior work experience in using Latency, skew and Duty cycle preservation by various techniques and CRPR reduction.
1 year of prior work experience in working on Global clock distribution involving Multi-Instance blocks and Hierarchical designs.
1 year of prior work experience in utilizing Clock timing and FEV analysis to minimize debug time at integration.

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game-texts

Work as a specialized SOC clock implementation engineer and manage a team of clock design engineers. Use engineering skills to define clock methodology for System on Chip, including clock structure, simulation model, and physical implementation for high performance low power CPU cluster, Memory modules and subsystems. Develop and maintain an efficient clock structure with low latency and skew. Analyze clock tree quality and provide guidance to improve quality. Engage with the SOC physical design team on the adoption of the clock methodology for high performance designs. Work with synthesis, place & route, STA, Spice, and other related analysis/verification tools for electrical engineering and design. Help engineer the CMOS circuit, focusing on low power design, electromigration (EM), voltage droop (IR), noise, design-for-manufacturing (DFM), and other related engineering design challenges.

Education:

Master’s or foreign equivalent in Electrical Engineering or related field

Experience:

7 years of experience in job offered or related occupation.

Special Requirements: Must have at least 1 year of prior work experience in each of the following

1. Clock Planning, Design, Execution, Clock timing, Clock FEV, Clock quality signoff and Power reduction.
2. Designing and developing workflow methodology to ensure seamless integration of design through multiple hierarchies.
3. Designing clocks ranging from 200MHz to 3GHz High-speed clocks for Cache modules/Memory Sub-systems/DDR/Fabrics and Display with ultra-low skews without sacrificing power.
4. Using Latency, skew and Duty cycle preservation by various techniques and CRPR reduction.
5. Working on Global clock distribution involving Multi-Instance blocks and Hierarchical designs.
6. Utilizing Clock timing and FEV analysis to minimize debug time at integration.

Telecommuting allowed for this position