Senior Staff Digital Design Engineer – Wireline PHYs

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

As a Digital IC Design Senior Staff Engineer with Marvell, you’ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking.

As a Senior Staff Digital Design Engineer you'll be focusing on system-level digital design and integration of wireline PHY IP for high-performance SoCs and ASICs. You will be responsible for architecting and implementing digital control, adaptation, DSP, and datapath logic enabling seamless PHY operation within larger system architectures, with an emphasis on embedded microcontroller integration, bus protocols, and system validation.

What You Can Expect

• Architect and implement RTL for digital control, DSP blocks, digital datapath, and adaptation engines of PHY IP targeting SerDes, Die-to-Die, and Parallel Optics applications.
• Design and verify bus interfaces (APB, AHB, AXI) and register maps for microcontroller communication and firmware control.
• Collaborate closely with system architects and firmware teams to optimize PHY integration into SoC and chiplet environments.
• Drive timing closure and ensure synthesis-friendly RTL targeting system-level constraints and goals, including DSP and datapath optimizations.
• Support system bring-up activities, validation planning, and post-silicon debug with a focus on system-level interactions involving digital datapath and DSP logic.
• Mentor junior engineers and contribute to improving design methodologies for PHY system integration, including DSP and datapath design best practices.

What We're Looking For

• Master’s degree +7 years or PhD +4 years in Electrical Engineering, Computer Engineering, or related fields.
• Strong RTL design expertise in Verilog/SystemVerilog, with a focus on digital control blocks, DSP, digital datapath, and bus protocols.
• Solid understanding of logic synthesis, static timing analysis (STA), constraints development, and timing closure at block and chip levels.
• Deep knowledge of CDC and RDC design principles.
• Experience integrating PHY digital blocks, including DSP and datapath modules, with embedded microcontrollers, including interrupt and event handling.
• Familiarity with scripting for design automation (Python, TCL, Perl).
• Proven problem-solving and debug experience at system level, including post-silicon validation, particularly for DSP and datapath components.
• Preferred: understanding of firmware-hardware co-design and system bring-up tools.

Expected Base Pay Range (USD)

124,420 - 186,400, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

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