Senior VLSI Physical Design Integration Engineer

NVIDIA is seeking an outstanding Senior VLSI Physical Design Integration Engineer to join our team, collaborating with USA, Israel, and India teams. This role involves contributing to the development of our networking product line from concept to tapeout. Key responsibilities include running integration flows, performing linting and connectivity checks, collaborating with front-end teams, managing cell libraries, optimizing synthesis workflows, and executing physical design flows from netlist to GDS, including STA and physical verification. The ideal candidate will also enhance tool automation and streamline workflows.

Must Have

• Run integration flows to build RTL and assemble logical units
• Perform linting checks and debug RTL and netlist-level issues
• Collaborate with front-end teams to resolve connectivity issues and implement design fixes
• Manage project-level cell library to ensure compatibility
• Run synthesis workflows and optimize for area, power, and timing
• Run physical design flow from netlist to GDS
• Perform STA, physical verification (LVS/DRC)
• Perform netlist checks and formal equivalence validation
• Enhance tool automation, streamline workflows, and document best practices
• BSEE / MSEE or equivalent experience
• Minimum 5+ years of experience in VLSI physical design implementation on 16nm, 7nm, 5nm or 3nm technology
• Able to assist in design flow development and debugging
• Validated strong power user of P&R, Timing analysis, Physical Verification and IR Drop Analysis CAD tools from Synopsys (ICC2/DC/PT/STAR/ICV), Cadence (Genus/Innovus/Tempus) and other major EDA companies
• Possess strong analytical and debugging skills

Good to Have

• Proficiency using Python
• Proficiency using Perl
• Proficiency using Tcl
• Proficiency using Make scripting

Perks & Benefits

• Equity
• Benefits

NVIDIA is seeking an outstanding Senior VLSI Physical Design Integration Engineer who is dedicated to collaborating closely with our teams in the USA, Israel, and India. As a valued member of our team, you will contribute to the development of our networking product line, from concept to tapeout. If you are hardworking and thrive on challenges, join us and make a significant impact!

What you'll be doing:

• Run integration flows to build RTL, run connectivity checks, and assemble logical units.
• Perform linting checks and debug RTL and netlist-level issues.
• Collaborate with front-end teams to resolve connectivity issues and implement design fixes to ensure physically-viable RTL netlists are delivered to downstream physical design flows.
• Project level cell library management to ensure compatibility between all workflows.
• Run synthesis workflows and optimize for area, power, and timing.
• Run physical design flow from netlist to GDS, perform STA, physical verification (LVS/DRC)
• Perform netlist checks and formal equivalence validation.
• Enhance tool automation, streamline workflows, and document best practices.

What we need to see:

• BSEE / MSEE or equivalent experience.
• Minimum 5+ years of experience in VLSI physical design implementation on 16nm, 7nm, 5nm or 3nm technology.
• Able to assist in design flow development and debugging.
• Already a validated strong power user of P&R, Timing analysis, Physical Verification and IR Drop Analysis CAD tools from Synopsys (ICC2/DC/PT/STAR/ICV), Cadence (Genus/Innovus/Tempus) and other major EDA companies.
• To be successful you should possess strong analytical and debugging skills.
• Proficiency using Python, Perl, Tcl, Make scripting is desired.
• Great teammate

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 212,750 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until January 10, 2026.

NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.