SoC Design Verification Engineer

36 Minutes ago • 5 Years +

Job Summary

Job Description

The SoC Design Verification Engineer will develop and verify pre-silicon DFx validation tests, create test plans for RTL validation, and run simulation models. This role involves debugging failing RTL tests, collaborating with architecture and design teams, and delivering validated DFx IP/SoC. The engineer will also partner with post-Silicon teams for test capability and support silicon diagnosis, while maintaining and improving verification infrastructure.
Must have:
  • Understand DFx architecture
  • Develop Pre-silicon DFx validation tests
  • Create test plans for RTL validation
  • Define and run simulation models
  • Find and implement corrective measures for failing RTL tests
  • Ensure security coverage
  • Drive technical reviews with design and architecture teams
  • Collaborate with SoC architects, microarchitects, full chip architects, RTL developers, post silicon, and physical design teams
  • Deliver validated DFx IP/SoC for simulation and post silicon usage
  • Partner with post-Silicon Team to enable DFx test capability in silicon
  • Support debug of any test content failures including silicon diagnosis in the post-Silicon environment
  • Maintain and improve existing functional verification infrastructure and methodology
  • Bachelor or Master's degree in Electronic, Electrical or Computer Engineering, or equivalent
  • At least 5 years of experience in DFX/RTL Design/integration verification
  • Experience in scripting proficiency (perl, python, etc)

Job Details

Job Description:

  • Understand DFx architecture and develop Pre-silicon DFx validation tests to verify design quality.
  • Create test plans for RTL validation, define and run simulation models, find and implement corrective measures for failing RTL tests, including regression and debug tests, to ensure security coverage.
  • Drives technical reviews of plans and proofs with design and architecture teams.
  • Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, post silicon, and physical design teams to improve verification of complex architectural and microarchitectural features.
  • Deliver validated DFx IP/SoC for simulation and post silicon usage.
  • Partner with post-Silicon Team to enable DFx test capability in silicon.
  • Support debug of any test content failures including silicon diagnosis in the post-Silicon environment.
  • Maintains and improves existing functional verification infrastructure and methodology.

Qualifications:

  • Bachelor of Engineering degree or a Master of Science degree in Electronic, Electrical or Computer Engineering, or equivalent with preferably at least 5 years of experience.
  • Hands-on experience in DFX/RTL Design/integration verification.
  • Experience in scripting proficiency (perl, python, etc) to automate design process and improve efficiency.
  • Ability to communicate well with counterparts and key stakeholders.

Job Type:

Experienced Hire

Shift:

Shift 1 (Malaysia)

Business group:

The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness that power Intel’s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

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