SOC Electrical Analysis Engineer

rivos

| Santa Clara, California, United States (Hybrid) | Full Time | 46 months ago

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Job Summary

Join a cutting-edge hardware startup in Silicon Valley as a Silicon EA Engineer. The company aims to reimagine silicon and create Risc-V based computing platforms to transform the industry. This role offers the chance to collaborate with talented engineers on designs that push performance, energy efficiency, and scalability. The work environment is described as fun, creative, and flexible, with a shared vision to build world-changing products. Responsibilities include developing Electrical Analysis methodology and infrastructure for verifying large HPC SoCs, performing full chip analysis debug and closure for IR, IVD, and EM for signal and power, providing input for floor planning, collaborating with technology and CAD teams, and designing and validating power distribution networks for optimal PPA in IPs.

Must Have

Develop Electrical Analysis methodology and infrastructure
Perform full chip analysis debug and closure (IR, IVD, EM)
Provide input to floorplan and guidance to implementation teams
Collaborate with Technology and CAD teams
Design and validate Power Distribution Networks
Experience with industry standard EA tools (Redhawk, Voltus)
Understanding of package modeling for power analysis
Expertise in EA convergence for high performance designs
Strong scripting skills in tcl and python
Ability to solve complex problems and communicate effectively
Self-starter and highly motivated
Ability to work cross-functionally under aggressive schedules

Job Description

Join a cutting-edge and well-funded hardware startup in Silicon Valley as a Silicon EA Engineer. Our mission is to reimagine silicon and create Risc-V based computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.

Responsibilities

Develop our Electrical Analysis methodology and infrastructure to enable the verification flow of large HPC SoCs
Perform full chip analysis debug and closure of all EA flows, including IR, IVD, EM for signal and power
Provide input to full chip floorplan and guidance to the implementation teams throughout the project to enable early convergence and final closure
Collaborate with Technology team and CAD partners to drive closure targets and signoff criteria
Design and validate Power Distribution Networks optimized for best PPA in specific IPs

Requirements

Experience with industry standard EA tools (Apache Redhawk, Cadence Voltus)
Understanding of package modeling techniques for full level power analysis
Expertise in EA convergence issues associated with high performance designs in advanced process nodes (static and dynamic IR driven timing closure)
Strong scripting skills in tcl and python
Ability and taste for solving complex problems, efficient written and verbal communication, excellent organization skills
Self starter and highly motivated
Ability to work cross-functionally with various teams and be productive under aggressive schedules