Timing Radio Integration Engineer

Do you have a passion for invention and self-challenge? Do you thrive on pushing the limits of what’s considered feasible. As part of a world class modem team, you’ll craft sophisticated groundbreaking embedded firmware that deliver more performance in our products than ever before. You’ll work across fields to transform improved hardware elements into a single, integrated design. Join us, and you’ll help us innovate new cellular technologies that continually outperform the previous iterations! The wireless Radio team architects, develop, and validates radio transceivers coordinated into sophisticated wireless SoCs. Our wireless organization is responsible for all aspects of wireless silicon development that transform the user experience at the product level. All of which is driven by an outstanding vertically coordinated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. As a Timing Radio Integration Engineer, you will be at the center of a wireless SoC design group with a critical impact on getting Apple’s groundbreaking wireless connectivity solutions into hundreds of millions of products!

As a Timing Integration Engineer, you will be a key member of the radio team, integrating and bringing the next-generation wireless SoCs into high-volume production at sophisticated CMOS technology nodes for Apple products.

• Defining and creating .libs for analog blocks for timing and power intent delivery to the SOC team. Using STA and CPI tools to verify and optimize these collaterals.
• Working closely with CAD teams on top level IP radio verification tapeout flows and releases to the SOC team.
• Using PTPX and other power analysis tools to characterize digital blocks’ current profiles. Using above timing tools to trade off timing and power requirements with appropriate standard cell flavors.
• Close interaction with the RFIC/AMS designers, modeling and DV teams in defining, modeling, and simulating digital blocks and their sequences within the transceiver.
• Working closely with the Radio SiVal team for a successful bring up of the chip, and support in the lab for debug and optimization when silicon is back.

• BS and a minimum of 10 years relevant industry experience
• Prior use of analog and digital timing closure tools like NanoTime and PrimeTime to identify relevant timing arcs and verify analog-to-digital signal interface high speed timing.
• Familiarity with custom analog blocks within the radio transceiver such as digital PLLs and RX/TX datapath IPs.
• Experience with Cadence Spectre analog design tools for running analog simulations as needed.

• MSEE with extensive experience for top radio level timing and digital verification.
• Digital Power Analysis tools such as PTPX to help evaluate digital radio blocks’ power profiles.
• Solid digital background in RTL design, synthesis and FE-STA to be able to work with digital teams to architect high speed data paths and DSPs that communicate with RF and analog sub-cells.
• Understanding of ATPG and DFT support for SOC scan debug chains and their timing to the radio sub-cells.
• Analog modeling & netlist verification tools such as Insight Analyzer and SimVision to verify signal integrity and connectivity at the radio level.

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