Job Description
Join a well-funded startup as an analog engineer leading the design of droop sensing, clocking, PLL, LDO, On-die VRs, and PMICs using the latest FinFET technology nodes. The company's mission is to reimagine silicon and disrupt high-performance computing platforms with RISC-V based chiplet designs. Responsibilities include design and specification development for advanced mixed-signal/analog circuits, close collaboration with system architects and verification engineers, behavioral modeling of analog blocks, and leading the development of analog blocks with external vendors, including integration and characterization efforts.
Good To Have:
- Developing behavior modeling
- IP design management or vendor management
Must Have:
- Design and specification development for analog blocks
- Behavioral modeling of analog blocks
- Collaboration with external vendors
- Strong track record in silicon IP development
- Deep understanding of analog circuits (bandgaps, PLLs, LDOs etc.)
- Analog design techniques
- Digital integration of analog IPs
- Device physics knowledge for analog IC design
- Lab characterization experience
- Production test plan development
- Excellent communication skills
- Team player
Join a well funded startup as an analog engineer leading the designs for droop sensing, clocking, PLL, LDO, On-die VRs and PMICs using latest finfet technology nodes. Our mission is to reimagine silicon and disrupt the high performance computing platforms with the RiscV based chiplet designs.
Responsibilities
- Responsible for design and spec development and design of analog blocks for advanced mixed-signal / analog circuits.
- Write detailed design specification and will be in close collaboration with the system architect, circuit designers and design verification engineers.
- Work on behavioral modeling of analog blocks and support design verification to ensure bug free silicon.
- Lead development of analog blocks in collaboration with external vendors and lead integration, test plan and characterization efforts.
Requirements
- Strong track record of architect, develop, verification and validation of complete silicon IPs
- Deep understanding of bandgaps, bias, opamps, switched-cap circuits, LDOs, PLLs, feedback and compensation techniques, DCDC converters
- In-depth knowledge and good understanding of analog design techniques.
- Experience in digital integration of analog IPs with chip level integration team
- Experience in developing behavior modeling a plus
- Experience IP design management or vendor management a plus
- Strong device physics knowledge as it applies to analog IC design
- Hand-on experience with IP lab characterization using spectrum analyzers, oscilloscopes, signal generators, etc.
- Experience in working with production test engineers to produce test plans and design for testability details
- Excellent communication skills
- Team player with an ability to encourage team members
Education & Experience
- MS (preferred in EE) plus 8 years
- PhD (preferred in EE) plus 5 years
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