Architecture Modeling Engineer

Job Description:

Perform semiconductor engineering design, development, and testing for products and devices in conjunction with product development for the semiconductor manufacturing industry. Responsible for pre-silicon performance modeling to cover IP RTL and SoCs. Involves development and integration of System C / C++ performance models under an industry standard Synopsys TLM based modeling framework. Design and develop C++ based component models as derived from IP block specifications. Integrate System C/C++ based components models for the purposes of SoC level, Subsystem level and IP level simulations towards derisking / improving the performance of the overall SoC and IP Architecture. Quantify and improve overall SoC performance by running use-cases, benchmarks, workloads and/or traffic loads on performance models, FPGA development boards, and/or silicon. Collaborate with systems and architecture leads to define customer use-cases and benchmarks. Collaborate with SoC performance verification teams to help a) define the pre-silicon SoC RTL derisk plans and b) assisting with the analysis of the performance data arising from the execution of these plans.

Qualifications:

Master’s degree in Computer Engineering, Electrical Engineering, Electronics Engineering, foreign equivalent or related field.

Required skills:

Position requires experience in:

• Programming in C/C++ or Python,
• Digital Integrated Circuit Design,
• Computer Architecture & Processor Design,
• Digital VLSI Testing,
• FPGA Information Processing Systems,
• Hardware Design Functional Verification,
• Verilog, System Verilog, and UVM, and
• SoC & IP RTL Design.