CPU Design Verification Sr Lead Engineer

1 Day ago • 3 Years +

Testing

Job Description

Qualcomm is seeking a Senior Lead Design Verification Engineer for high-performance, low-power CPUs in Bangalore. This role focuses on power management verification, including Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management, and throttling. The engineer will collaborate with design, verification, system architects, software, and SoC teams to develop comprehensive test plans. Responsibilities include using simulation and formal verification, writing checkers and assertions, developing stimulus, and verifying power intent with UPF. Debugging failures in simulation, emulation, and Silicon is also a key aspect of the role.

Good To Have:

Good Understanding of CPU architectures and CPU micro-architectures.
In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture.
Experience with advanced verification techniques such as formal and assertions is a plus.
Knowledge and verification experience in DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump is a plus.

Must Have:

Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling.
Work closely with design/verification teams within CPU to develop comprehensive test plan.
Use simulation and formal verification methodologies to execute test plans.
Write checkers, assertions and develop stimulus.
Verify power intent through use of methodologies like UPF.
Work closely with system architects, software teams and Soc team to validate system use cases.
Work closely with emulation team to enable verification on emulators and FPGA platforms.
Debug and triage failures in simulation, emulation and/or Silicon.
Experience in power management verification.
Implementation of assembly and C language embedded firmware.
Experience in C/C++, scripting languages, Verilog/system Verilog.
Strong understanding of power management features in CPUs and CPU based Socs.
Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc.

Perks:

Qualcomm offers a world-class health benefit option providing world-class coverage to employees and their eligible dependents.
Our programs are designed to help employees build and prepare for a financially secure future.
Our self and family resources help you build emotional/mental strength and resilience, as well as define your purpose — in life and at work.
Qualcomm’s wellbeing programs and resources offer support to help employees Live+Well and Work+Well, so they can unlock their full potential at home, at work, and everywhere between.

Add these skills to join the top 1% applicants for this job

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Job Posting Date

2025-09-17

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Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

Qualcomm is hiring strong DV engineers to verify high performance and low power CPUs in Bangalore. Please forward your profiles if you meet the requirement.

Roles and Responsibilities

Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling.
Work closely with design/verification teams within CPU to develop comprehensive test plan.
Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus.
Verify power intent through use of methodologies like UPF.
Work closely with system architects, software teams and Soc team to validate system use cases.
Work closely with emulation team to enable verification on emulators and FPGA platforms.
Debug and triage failures in simulation, emulation and/or Silicon.

Minimum Qualifications:

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
BE/BTech degree in CS/EE with 3+ years’ experience.
Experience in power management verification.
Implementation of assembly and C language embedded firmware.
Experience in C/C++, scripting languages, Verilog/system Verilog.
Strong understanding of power management features in CPUs and CPU based Socs.
Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc.

Preferred Requirements:

Good Understanding of CPU architectures and CPU micro-architectures.
In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture
Experience with advanced verification techniques such as formal and assertions is a plus
Knowledge and verification experience in DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump is a plus

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