Senior Manager, ASIC Design Enablement

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What You’ll Do

The Senior Manager, ASIC Design Enablement involves working on cutting edge ASIC’s in advanced nodes involving Monolithic / 2.5D / 3D / Chiplet based designs . The candidate will be working with external customers and internal teams and manage the end to end design implementation from spec to siliconm chip-level floorplan, budgeting and partitioning, 2.5 D interposer planning , 3DIC early thermal analysis, chiplet planning and integration.

Location: Onsite at our San Jose headquarters 5 days a week with an average of 15-20% travel per year.

Reports to: Senior Director, ASIC Engineering

Job ID: 42337

• Solid experience in full chip prototype solution , memory selection, die size estimation, trade off analysis monolithic vs 2.5D vs chiplet based designs
• Solid understanding of DFT strategies , streaming scan fabric , 1838 protocol
• Solid experience in high speed CTS , timing closure on highly complex SoC
• Solid experience in using place and route tools and achieving the best PPA of the full-chip physical design
• Solid experience with advanced nodes like 3,4,5,7 nm
• Solid knowledge of NOC ( Network on Chip from Netspeed / Arteris ) Physical Implementation
• Solid experience of writing timing constraints , integrating IP constraints and working closely with STA and logic design engineers to close timing
• Solid experience in PDN build and power integrity analysis flow (static/dynamic IR-drop analysis)
• Solid experience in EM analysis and fix
• Solid experience in physical verification flow including DRC, LVS, PERC and DFM rule checking and fix
• Solid Experience in project management ASIC with good understanding of RTL , Synthesis, DFT , Design Verification , Physical Design , STA , Physical Verification , Package, Co-Package Optics , Test , Assembly, Silicon Bring up etc
• Customer technical intereaction, memory selection, IP Integration discussions with design team.
• Project Management of ASIC’s.
• Samsung design metohodology support for ASIC Customers.
• Complete other responsibilities as assigned.

What You Bring

• Bachelors in Electrical Engineering or related Physical Science with 20+ years of experience or Masters in Electrical Engineering or related Physical Science with 18+ Years of Industry Experience or PhD in Electrical Engineering or related Physical Science with 15+ years of years.
• Direct experience in ASIC or chip design, with significant hands on experience in large complex projects involving HPC ( AI / ML / Bufferless HBM / ) Monolithic . 2.5D / 3D / Chiplet based designs.
• Strong Knowledge in hierarchical physical design methodologies, chip floorplan, building on-chip PDN, partitioning, place-and-route, IR-drop analysis, EM analysis and physical verification, package Co-Optics. 
• Comfortable working with internal and managing 3^rd party teams.
• Highly passionate and energetic.
• Excellent communication skills
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

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