SOC Physical Design Engineer

3 Years ago • All levels

Software Development & Engineering

Job Description

This full-time SOC physical implementation role involves unit-level to chip-level physical design functions including P&R, timing, floorplan, clocking, electrical analysis, and power. Responsibilities include owning block-level design from RTL-to-GDSII, driving synthesis, floor-planning, place & route, timing closure, and signoff. The role requires extensive work with Micro-architects for feasibility studies and PPA tradeoffs, developing physical design methodologies, and collaborating with cross-functional teams for implementation and validation. This includes running signoff flows like Timing, Power, EM/IR, and PDV.

Must Have:

Own block level design from RTL-to-GDSII
Work with Micro-architects for PPA tradeoffs
Develop physical design methodologies
Signoff flows like Timing, Power, EM/IR, PDV
Knowledge of synthesis, place & route, analysis tools
Logic & physical design principles for low-power designs
Scripting in Unix, Perl, Python, or TCL
Understanding of device physics and deep sub-micron technologies
Knowledge of Verilog and SystemVerilog
Excellent problem-solving and communication skills

Add these skills to join the top 1% applicants for this job

cad-computer-aided-design

unity

unix

level-design

python

perl

Positions are open for full-time SOC physical implementation from unit level to chip level, involving all aspects of physical design functions such as P&R, timing, floorplan, clocking, electrical analysis, and power.

Responsibilities

Own block level design from RTL-to-GDSII and drive synthesis, floor-planning, place & route, timing closure, and signoff.
Work extensively with Micro-architects to perform feasibility studies and explore performance, power & area (PPA) tradeoffs for design closure.
Develop physical design methodologies and customize recipes across various implementation steps to optimize PPA.
Work with a multi-functional engineering team to implement and validate physical design by running all signoff flows such as Timing, Power, EM/IR, PDV.

Requirements

Knowledge using synthesis, place & route, analysis and verification CAD tools.
Familiarity with logic & physical design principles to drive low-power & higher-performance designs.
Knowledge of scripting in some of these languages: Unix, Perl, Python, and TCL.
Good understanding of device physics and experience in deep sub-micron technologiesKnowledge of Verilog and SystemVerilog.
Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
Ability to work well in a team and be productive under aggressive schedules.