This full-time SOC physical implementation role involves unit-level to chip-level physical design functions including P&R, timing, floorplan, clocking, electrical analysis, and power. Responsibilities include owning block-level design from RTL-to-GDSII, driving synthesis, floor-planning, place & route, timing closure, and signoff. The role requires extensive work with Micro-architects for feasibility studies and PPA tradeoffs, developing physical design methodologies, and collaborating with cross-functional teams for implementation and validation. This includes running signoff flows like Timing, Power, EM/IR, and PDV.