Sr. Staff Static Timing Analysis (STA) Engineer

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

The Design Center Engineering Physical Design team at Marvell in Santa Clara is seeking a Sr. Staff Static Timing Analysis (STA) Engineer to contribute to a wide range of innovative projects—from artificial intelligence and machine learning to advanced wired and wireless infrastructure—using the latest technology nodes.

Our team leverages cutting-edge EDA tools to solve complex challenges and ensure our designs meet critical performance, power, and area (PPA) goals. This role involves close collaboration with Physical Design, Design for Test (DFT), and other cross-functional teams across both local and global sites.

If you're looking to apply your STA expertise in a dynamic and forward-thinking environment, this is a great opportunity to explore.

What You Can Expect

• This position is a full-time in-office role located in Santa Clara. Relocation will be required.
• Perform timing analysis and closure on complex partitions.
• Develop and implement timing closure and logical ECO’s.
• Interface with the RTL design team to drive design modifications to resolve congestion and timing issues.
• Work with the global timing team in debugging/resolving any block level timing issues seen at full chip.
• Experienced with the balancing the trade-offs of Performance, Power, and Area.
• Maintain, enhance, and support Marvell’s timing and/or power flows.
• Test and maintain chip end-to-end flows, with specific focus on timing and/or power.
• Interact with tool vendors to drive tool fixes and improvements in support of on-going and planned CAD activities.
• Perform tool evaluations of new vendor tools and functions.

What We're Looking For

• BS/MS in EE/CS with 6+ years of hands-on experience in CAD back-end physical design and verification. Familiar with hierarchical physical design strategies, methodologies and deep sub-micron technology issues like N5/N3/N2. Familiar with ASIC design flow, Verilog HDL, synthesis and timing closure.
• Proven track records of handling chip level P&R independently and taping out complex SOC chips under tight schedule pressure.
• Strong proficiency of PD optimization and Routing such as floorplanning, placement, clocking, and routing.
• Must be programming-minded, solid coding experience in Makefile/Tcl/Perl.
• Detail oriented, self-motivated team worker, good verbal and written communication skills.
• Must be a power user of Cadence suite (Genus, Innovus) or Synopsys suite (fusion compiler).
• Solid knowledge and experience on static timing analysis (Tempus, or PrimeTime), EM/IR-Drop/crosstalk analysis (Voltus, Redhawk), extraction (QRC, StarRC), formal or physical verification (LEC, Formality, Calibre).
• Good communication skills and self-discipline contributing to a team environment.

Expected Base Pay Range (USD)

124,420 - 186,400, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

At Marvell, we offer a total compensation package with a base, bonus and equity. Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity

As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.

Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process.

Export Control Notice

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.