3DIC Principal Application Engineer
Job Description
- Support 3DIC design partitioning, floor planning, IP placement, TSV placement and power-grid planning & design.
- Generate 3D stacking, hybrid bonding pad and u-bump map.
- Improve design flows and methodologies for advanced technology nodes.
- Work closely with Design, CAD and physical implementation teams, as well as R&D.
- Develop scalable & sometimes custom solutions, streamline & automate workflows.
- Utilize scripting languages such as Tcl and Python for automation.
- Identify design, tool or flow issues and facilitate in resolution.
- 8+ years of experience in Power Signoff and Physical Implementation of designs at 20nm and below, on actual tapeouts.
- Power analysis, optimization and IR-aware implementation experience.
- Familiarity with digital Place and Route methodology, static timing analysis.
- Proficiency in at least one scripting language such as perl or TCL.
- Excellent debugging skills and ability to separate critical issues.
- Superior communication skills, an outgoing personality and ability to build rapport with the customer.
- Paid vacation
- Paid holidays
- 401(k) plan with employer match
- Employee stock purchase plan
- Medical plan options
- Dental plan options
- Vision plan options
- Incentive compensation (bonus, equity)
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
As a senior member of the top performing team at Cadence this person will be responsible for guiding the design implementation solutions and flow development of 3DIC for various top semiconductor companies of the world. They will interact with various teams, including physical design implementation & Sign-Off analysis and Verification teams of Customers, as well as R&D teams for development of most efficient and reliable semiconductor products.
Key Responsibilities:
- Physical Implementation: The person will be responsible to support 3DIC design partitioning, floor planning, IP placement, TSV placement and power-grid planning & design
- 3D Stacking & Packaging: Generate 3D stacking, hybrid bonding pad and u-bump map
- Design Flow Optimization: Improve design flows and methodologies for advanced technology nodes
- Collaboration & Communication: Work closely with Design, CAD and physical implementation teams, as well as R&D to provide adequate solutions & support
- EDA Tool Expertise & Scripting/Automation: Develop scalable & sometimes custom solutions, streamline & automate workflows. Utilize scripting languages such as Tcl and Python for automation
- Problem Solving: Identify design, tool or flow issues and facilitate in resolution
Requirements
- Bachelors in Electrical/Computer Engineering required; 8+ years of experience in Power Signoff and Physical Implementation of designs at 20nm and below, on actual tapeouts required.
- Power analysis, optimization and IR-aware implementation experience is a must.
- Must be familiar with digital Place and Route methodology, static timing analysis and at least one scripting language such as perl or TCL.
- Must have excellent debugging skills and an ability to separate out the critical issues from trivial ones.
- Must possess superior communication skills, an outgoing personality and an ability to build a rapport with the customer
- Be proud and passionate about the work you do. Together, our One Cadence -- One Team culture drives our success.
The annual salary range for California is $123,200 to $228,800. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
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