ASIC Chip Lead

broadcom

10+ Years | San Jose, California, United States (On Site) | Full Time | 1 day ago

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Job Summary

Broadcom is seeking a highly experienced Principal ASIC Chip Lead to develop cutting-edge System-on-Chip (SoC) solutions. This key role requires a deep, end-to-end understanding of the entire ASIC architecture, design, and verification flow—from initial concept and RTL development through GDSII tape-out and into mass production. The lead will manage cross-functional teams, define micro-architecture, and collaborate with various engineering teams to bring silicon into mass production.

Must Have

Manage cross-functional project teams and interface with tier-1 customers.
Define micro-architecture for design blocks and develop Verilog RTL.
Perform frontend tool checks for linting, clock domain crossing, Low Power design, and UPF/CPF flow.
Collaborate with verification team on test plan, coverage plan, and coverage closure.
Work with physical design team on design constraints and timing closure.
Help firmware and systems teams with bring-up on FPGA and Silicon platforms.
Work with operations team to bring silicon into mass production.
BSEE with 12+ years or MSEE with 10+ years experience in Microarchitecture & RTL Design.
Detailed understanding of RTL design, logic synthesis, static timing analysis, design verification, clock domain crossing, and low power design techniques.
Strong Logic Design & RTL Design Skills using Verilog HDL.
Excellent written and verbal communication skills.
Ability to understand engineering and microarchitecture specifications.
Knowledge and experience of ARM-based SoC, DSP-based design, and analog interfaces.
Experience with peripherals like I2C, SPI, SPMI, UART, Asynchronous interface designs, Digital Signal Processing, Memory Controllers, and interconnect protocols such as AHB, AXI.
Experience with Low Power Design & design verification techniques, Multiple Power domains, UPF/CPF understanding and usage.
Good knowledge of EDA tools.

Good to Have

Solid understanding of communication basics.
Experience with implementation of arithmetic hardware (fixed point, floating point, transcendental operations).
Familiarity with signal processing and numerical analysis tools like MATLAB.
Experience and understanding of DSP Designs using MATLAB/Simulink.
Ability to work in a lab with logic analyzers and oscilloscopes during Silicon/FPGA bring up.
Experience with C/C++ and Scripting languages (Perl/Tcl).

Perks & Benefits

Discretionary annual bonus
Equity
Medical, dental and vision plans
401(K) participation including company matching
Employee Stock Purchase Program (ESPP)
Employee Assistance Program (EAP)
Company paid holidays
Paid sick leave
Vacation time
Paid Family Leave and other leaves of absence

Job Description

Broadcom is seeking a highly experienced and accomplished Principal ASIC Chip Lead to lead the development of cutting-edge System-on-Chip (SoC) solutions. This key role requires a deep, end-to-end understanding of the entire ASIC architecture, design, and verification flow—from initial concept and RTL development through GDSII tape-out and into mass production.

Responsibilities:

Manage cross-functional project teams while interfacing directly with a tier-1 customer. Must have soft skills to manage and diffuse high stakes.
Work with architecture team to define micro-architecture for various design blocks & subsequently Verilog RTL development
Run various frontend tools to check for linting, clock domain crossing, Low Power design, and checks using UPF/CPF flow
Work with verification team to collaborate on test plan, coverage plan, and coverage closure
Work with physical design team on design constraints and timing closure
Work with firmware and systems team and help with bring-up on FPGA and Silicon platforms
Work with operations team to bring silicon into mass production
Willing to learn new areas and flexible in taking on any of the above tasks to help meet project goals

Required Qualifications:

BSEE with 12+ years of experience or MSEE with 10+ YEARS experience in Microarchitecture & RTL Design
Detailed understanding of RTL design, logic synthesis, static timing analysis, design verification, clock domain crossing, and low power design techniques
Strong Logic Design & RTL Design Skills using Verilog HDL
Excellent written and verbal communication skills
Ability to understand engineering and microarchitecture specifications
Knowledge and experience of ARM-based SoC, DSP-based design, understanding of analog interfaces and designs is a definite advantage
Experience with peripherals such as I2C, SPI, SPMI, UART, Asynchronous interface designs, Digital Signal Processing, Memory Controllers, peripherals, and interconnect protocols such as AHB, AXI, etc.
Experience with Low Power Design & design verification techniques, Multiple Power domains, UPF/CPF understanding and usage
Good knowledge of EDA tools
Willingness to work on any design tools/flow/methodologies, including Design-Verification as needed during project development and not strictly limited to RTL design work

Desired Skills:

Solid understanding of communication basics
Experience with implementation of arithmetic hardware (fixed point, floating point, transcendental operations)
Familiar with signal processing and numerical analysis tools like MATLAB
Experience and understanding of DSP Designs using MATLAB/Simulink is a definite advantage, but not limited to DSP designs
Able to work in a lab with logic analyzers and oscilloscopes during Silicon/FPGA bring up
Experience with C/C++ and Scripting languages (Perl/Tcl)

8 Skills Required For This Role

Cross Functional Communication Cpp Game Texts Test Coverage Fpga Matlab Perl

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