CPU Physical Design role involving P&R, timing, floorplan, clocking, and power. Must have experience with synthesis, place & route, and logic & physical design principles. Knowledge of CPU Core & L2 microarchitecture, scripting languages (Unix, Perl, Python, TCL), and deep sub-micron technologies preferred.
Must have:
Synthesis & P&R
Logic & Physical
CPU Core & L2
Scripting Languages
Good to have:
Deep Sub-micron
Device Physics
Verilog & SystemVerilog
Multi-functional Team
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Positions are open for full-time in the areas of CPU physical design from unit level to chip level, involving all aspects of physical design functions such as P&R, timing, floorplan, clocking, and power.
Responsibilities
Own block level design of CPU Core/L2 blocks from RTL-to-GDSII and drive synthesis, floor-planning, place & route, timing closure, and signoff.
Work extensively with Micro-architects to perform feasibility studies and explore performance, power & area (PPA) tradeoffs for design closure.
Develop physical design methodologies and customize recipes across various implementation steps to optimize PPA.
Work with a multi-functional engineering team to implement and validate physical design by running all signoff flows such as Timing, Power, EM/IR, PDV.
Requirements
Knowledge using synthesis, place & route, analysis and verification CAD tools.
Familiarity with logic & physical design principles to drive low-power & higher-performance designs.
Knowledge of CPU Core & L2 microarchitecture will be beneficial.
Knowledge of scripting in some of these languages: Unix, Perl, Python, and TCL.
Good understanding of device physics and experience in deep sub-micron technologiesKnowledge of Verilog and SystemVerilog.
Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
Ability to work well in a team and be productive under aggressive schedules.
Education and Experience
PhD, Master’s Degree or Bachelor’s Degree in technical subject area.
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