Digital Design Engineer

11 Minutes ago • 3 Years +

Design

Job Description

This role, based in Manila, involves collaborating with IC Design and Product Definition teams to develop digital elements for mixed-signal products at Power Integrations. Key responsibilities include designing functional digital blocks, contributing to ASICs from definition to production, supporting product architecture, completing RTL design in SystemVerilog, creating test benches for verification, performing digital synthesis, defining and implementing DFT architecture, generating documentation, and supporting silicon evaluation and product validation activities.

Must Have:

MSc/MEng or PhD in Electronics Engineering or related subject
Minimum 3 years experience in digital IC design using standard cell libraries
Familiarity with fully synthesised digital design flow with RTL and logic synthesis
Good knowledge of best-practice digital design methods
Good knowledge of SystemVerilog standard and scripting languages such as TCL
Familiarity with constraints and automatic place-and-route flow for physical design
Understanding of production test and experience with design methods to maximize test coverage (e.g., scan)
Experience with design techniques for optimising digital power consumption
Experience debugging digital functions in a lab using test equipment (e.g., mixed-signal oscilloscopes)
Experience producing accurate and complete documentation

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problem-solving

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Description

Description:

Based in our Manila office you will work closely with colleagues in both the IC Design and Product Definition teams to provide solutions required for the digital elements of the mixed signal products developed by Power Integrations. This will include suitable verification of the digital functions at the block-level and system-level.

Education & Experience:

MSc/MEng or PhD in Electronics Engineering or related subject.
Minimum 3 years experience in digital IC design using standard cell libraries.

Requirements:

Be familiar executing designs via a fully synthesised digital design flow with RTL and logic synthesis.
Have good knowledge and understanding of best-practice digital design methods.
Have good knowledge of the SystemVerilog standard and scripting languages such as TCL.
Be familiar with the use of constraints and the automatic place-and-route flow for the physical design.
Understand the importance of production test and have experience of design methods to maximize test coverage such as scan.
Have experience of design techniques for optimising digital power consumption.
Have experience of debugging digital functions in a lab using suitable test equipment (e.g. mixed-signal oscilloscopes).
Have experience producing accurate and complete documentation.

Main Responsibilities:

Development of functional digital blocks and contribution to complete mixed signal ASICs from definition to full production maturity.
Support the Product Definition team with feasibility study, product architecture definition and digital blocks design for FPGA emulation.
Complete RTL design in SystemVerilog of digital functions to meet all specification requirements.
Create suitable block-level test benches for comprehensive verification of all digital blocks.
Create suitable behavioural models and top-level test benches for comprehensive verification and regression of all system-level functions and production test functions.
Complete digital synthesis with suitable physical constraints to meet all PPA requirements.
Define and implement DFT architecture. Perform scan insertion, ATPG and insert test points to achieve the required test coverage.
Generate all necessary design documentation and participate in design reviews.
Support silicon evaluation and all product validation activities working with Product, Quality and Test Engineering up to production ramp-up.
Contribute to Technology Process and Design Methodology improvements.