DSP- Senior Lead Physical Design Engineer

Qualcomm

4+ Years | Noida, Uttar Pradesh, India (On Site) | Full Time | 2 months ago

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Job Summary

As a Senior Lead Physical Design Engineer at Qualcomm, you will plan, design, optimize, verify, and test DSP electronic systems. This role requires extensive hands-on experience in Physical Design (PnR) steps including Floorplanning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, ECO implementation, and DRC closure. You will also apply expertise in high-frequency design, advanced tech nodes, PG-Grid optimization, and custom clock tree implementations, collaborating with cross-functional teams to develop cutting-edge products.

Must Have

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
5+ years hands-on experience of different PnR steps including Floorplanning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, Post route optimization, ECO implementation and DRC closure.
Well versed with high frequency design & advanced tech node implementations.
In depth understanding of PG-Grid optimization, including identification of high vs low current density paths & layer/via optimization, Adaptive PDN experience.
In depth knowledge of custom clock tree including H-tree, SPINE, Multi-point CTS, Clock metrics optimization through tuning of CTS implementation.
Well versed with tackling high placement density/congestion bottlenecks.
In depth knowledge of PnR tool knobs/recipes for PPA optimization.
Experience in automation using Perl/Python and tcl.
Good communication skills and ability & desire to work in a cross-site cross-functional team environment.

Perks & Benefits

Qualcomm offers a world-class health benefit option providing world-class coverage to employees and their eligible dependents.
Our programs are designed to help employees build and prepare for a financially secure future.
Our self and family resources help you build emotional/mental strength and resilience, as well as define your purpose — in life and at work.
Qualcomm’s wellbeing programs and resources offer support to help employees Live+Well and Work+Well, so they can unlock their full potential at home, at work, and everywhere between.

Job Description

Job Posting Date

2025-09-05

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Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications:

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

5+ years hands-on experience of different PnR steps including Floorplanning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, Post route optimization, ECO implementation and DRC closure
Well versed with high frequency design & advanced tech node implementations
In depth understanding of PG-Grid optimization, including identification of high vs low current density paths & layer/via optimization, Adaptive PDN experience
In depth knowledge of custom clock tree including H-tree, SPINE, Multi-point CTS, Clock metrics optimization through tuning of CTS implementation.
Well versed with tackling high placement density/congestion bottlenecks
In depth knowledge of PnR tool knobs/recipes for PPA optimization
Experience in automation using Perl/Python and tcl
Good communication skills and ability & desire to work in a cross-site cross-functional team environment.

Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

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If you would like more information about this role, please contact Qualcomm Careers.