Lead Design Engineer - Verification

Cadence is seeking a skilled VLSI Design Verification Engineer with 3–5 years of experience to join their team in Shanghai. This role involves supporting SOC design projects, developing and executing verification plans for SOC and IP blocks, and performing RTL verification using UVM and SystemVerilog. The ideal candidate will collaborate with design teams to debug issues, optimize strategies, and ensure comprehensive test coverage, while also bridging communication between local and global stakeholders.

Must Have

• Develop and execute verification plans for SOC and IP blocks.
• Perform RTL verification using industry-standard methodologies (e.g., UVM, SystemVerilog).
• Collaborate with design engineers to address complex debug issues and optimize verification strategies.
• Work closely with customer and internal engineering teams to deliver high-quality support and service.
• Participate in coverage analysis, regression testing, and closure of verification goals.
• Contribute to the development and enhancement of verification environments and reusable testbenches.
• Bachelor’s or Master’s degree in Electrical/Computer Engineering or related field.
• 3–5 years of experience in VLSI/SOC design verification.
• Strong expertise in System Verilog, UVM, and Verification tools.

Good to Have

• Hands-on experience in any protocol like AMBA, PCIe, USB, MIPI or DDR/LPDDR.
• ARM/RISC-V Processor integration experience.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Responsibilities:

Looking for a skilled VLSI Design Verification Engineer with 3–5 years of hands-on experience to join our team supporting SOC design projects for leading customers. The ideal candidate will collaborate closely with design and verification teams to ensure comprehensive test coverage, robust verification methodology, and seamless project execution. Will play a key role in bridging communication between local teams and global stakeholders. Hands-on experience in any protocol like AMBA, PCIe, USB, MIPI or DDR/LPDDR. ARM/RISC-V Processor integration experience preferred.

• Develop and execute verification plans for SOC and IP blocks, ensuring design intent and testability.
• Perform RTL verification using industry-standard methodologies (e.g., UVM, SystemVerilog).
• Collaborate with design engineers to address complex debug issues and optimize verification strategies.
• Work closely with customer and internal engineering teams to deliver high-quality support and service.
• Participate in coverage analysis, regression testing, and closure of verification goals.
• Contribute to the development and enhancement of verification environments and reusable testbenches.

Requirements:

• Bachelor’s or Master’s degree in Electrical/Computer Engineering or related field with 3–5 years of experience in VLSI/SOC design verification.
• Strong expertise in System Verilog, UVM, and Verification tools.

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About Us

Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.

Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.