PCIe Design Engineer

Seeking an experienced PCIe Design Engineer to join our ASIC Product Division team. This role involves designing, implementing, and optimizing PCIe designs for complex SoC designs, collaborating with cross-functional teams. Key responsibilities include integration of PCIe controllers with other IPs, designing and implementing PCIe designs supporting various protocols like PCIe, CXL, and AMBA/AXI, performance analysis, and troubleshooting design and simulation issues.

Must Have

• Design Integration: Integration of PCIe controllers with other IP’s like Serdes, AXI bridges, and auxiliary IP’s.
• Protocol Expertise: Design and implementation of PCIe designs that support various protocols such as PCIe, CXL and AMBA/AXI.
• Performance Analysis: PCIe performance analysis to identify bottlenecks and areas for improvement as per customer requirements.
• Troubleshooting: Identify and resolve issues in PCIe design and simulation.
• Proficient in PCIe design integration and optimization techniques.
• Strong understanding of digital design principles and SoC understanding.
• Experience with hardware description languages (HDLs) such as Verilog, System-Verilog.
• Knowledge of RTL simulation tools and Verification environments (e.g., Cadence, Synopsys, UVM).
• Expertise in various communication protocols such as PCIe, CXL, and Amba/AXI.
• Bachelor’s or Master’s degree in Electronics and communication Engineering or a related field.
• 6 to 8 years of experience.

Good to Have

• Knowledge of PCIe Gen-4/5/6/7 protocol skills.
• Knowledge of ASIC design flows.
• Familiarity with scripting languages (e.g., Python, Perl).
• Synthesis Tools like (DC/DC-NXT) or Fusion compiler.
• Synthesis Constraints and Timing Concepts (STA).
• Spyglass (lint, DFT, PM, CLK/RST, CDC/RDC).
• Formal Verification check like Formality or Conformal LEC.

Job Summary:

Seeking an experienced PCIe Design Engineer to join our ASIC Product Division team. The ideal candidate will have a deep understanding of design integration skills and various communication protocols such as PCIe, CXL and AMBA/AXI. This role involves designing, implementing, and optimizing PCIe designs for complex SoC (System on Chip) designs, collaborating with cross-functional teams.

Key Responsibilities:

• Design Integration: Integration of PCIe controllers with other IP’s like Serdes, AXI bridges, and auxiliary IP’s.
• Protocol Expertise: Design and implementation of PCIe designs that support various protocols such as PCIe, CXL and AMBA/AXI.
• Performance Analysis: PCIe performance analysis to identify bottlenecks and areas for improvement as per customer requirements.
• Troubleshooting: Identify and resolve issues in PCIe design and simulation.

Primary Skills

• Proficient in PCIe design integration and optimization techniques.
• Strong understanding of digital design principles and SoC understanding.
• Experience with hardware description languages (HDLs) such as Verilog, System-Verilog.
• Knowledge of RTL simulation tools and Verification environments (e.g., Cadence, Synopsys, UVM).
• Expertise in various communication protocols such as PCIe, CXL, and Amba/AXI.

Soft Skills

• Excellent problem-solving and analytical skills.
• Strong communication and collaboration abilities.
• Attention to detail and a commitment to quality.
• Enthusiasm for research and development.

Preferred Skills:

• Knowledge of PCIe Gen-4/5/6/7 protocol skills.
• Knowledge of ASIC design flows.
• Familiarity with scripting languages (e.g., Python, Perl).
• Synthesis Tools like (DC/DC-NXT) or Fusion compiler.
• Synthesis Constraints and Timing Concepts (STA).
• Spyglass (lint, DFT, PM, CLK/RST, CDC/RDC).
• Formal Verification check like Formality or Conformal LEC.

Qualifications:

Education: Bachelor’s or Master’s degree in Electronics and communication Engineering or a related field.

Experience: 6 to 8 years of experience