PCIe Design Engineer - Principal

Broadcom is seeking an experienced PCIe Design Engineer for its ASIC Product Division. The role involves designing, implementing, and optimizing PCIe designs for complex SoCs, with a deep understanding of design development, integration skills, and communication protocols like PCIe, CXL, and AMBA/AXI. Key responsibilities include integrating PCIe controllers with other IPs, ensuring seamless SoC communication, performing performance analysis, and collaborating with cross-functional teams to meet customer requirements and performance goals.

Must Have

• Design and integrate PCIe controllers with Serdes, AXI bridges, and auxiliary IPs.
• Implement PCIe designs supporting PCIe, CXL, and AMBA/AXI protocols.
• Ensure seamless PCIe interface communication within overall SoC design.
• Conduct PCIe performance analysis to identify bottlenecks.
• Collaborate with software, implementation, SOC, and verification teams.
• Troubleshoot and resolve issues in PCIe design and simulation.
• Proficiency in PCIe design integration and optimization techniques.
• Strong understanding of digital design principles and SoC.
• Experience with Verilog and System-Verilog HDLs.
• Knowledge of RTL simulation tools and Verification environments (Cadence, Synopsys, UVM).
• Expertise in PCIe, CXL, and Amba/AXI communication protocols.

Good to Have

• Experience with PCIe Gen-4/5/6/7 protocol skills.
• Knowledge of ASIC design flows.
• Familiarity with scripting languages (Python, Perl).
• Experience with version control systems (Design-sync, Git).
• Background in PCIe design, PCIe protocols, Serdes concepts, low-power design and optimization.
• Synthesis Tools like (DC/DC-NXT) or Fusion compiler.
• Synthesis Constraints and Timing Concepts (STA).
• Spyglass (lint, DFT, PM, CLK/RST, CDC/RDC).
• Formal Verification check like Formality or Conformal LEC).

Job Summary:

We are seeking an experienced PCIe Design Engineer to join our ASIC Product Division team. The ideal candidate should have a deep understanding of design development and integration skills, and various communication protocols such as PCIe, CXL and AMBA/AXI. This role involves designing, implementing, and optimizing PCIe designs for complex SoCs and collaborating with cross-functional teams.

Key Responsibilities:

· Design Integration: Integration of PCIe controllers with other IP’s like Serdes, AXI bridges, and auxiliary IP’s.

· Protocol Expertise: Design and implementation of PCIe designs that support various protocols such as PCIe, CXL and AMBA/AXI.

· SOC understanding: Understanding of PCIe interface for overall SoC design, ensuring seamless communication between various IP blocks and subsystems.

· Performance Analysis: PCIe performance analysis to identify bottlenecks and areas for improvement as per customer requirements.

· Collaboration: Work closely with software, implementation, SOC, and verification teams to ensure that PCIe designs meet customer requirements and performance goals.

· Troubleshooting: Identify and resolve issues in PCIe design and simulation.

Primary Skills

· Proficient in PCIe design integration and optimization techniques.

· Strong understanding of digital design principles and SoC understanding.

· Experience with hardware description languages (HDLs) such as Verilog, System-Verilog

· Knowledge of RTL simulation tools and Verification environments (e.g., Cadence, Synopsys, UVM).

· Expertise in various communication protocols such as PCIe, CXL, and Amba/AXI.

Soft Skills

· Excellent problem-solving and analytical skills.

· Strong communication and collaboration abilities.

· Ability to work independently and in a team environment.

· Attention to detail and a commitment to quality.

· Enthusiasm for research and development.

Preferred Skills:

· Experience with PCIe Gen-4/5/6/7 protocol skills

· Knowledge of ASIC design flows.

· Familiarity with scripting languages (e.g., Python, Perl).

· Experience with version control systems (e.g., Design-sync, Git).

· Background in PCIe design, PCIe protocols, Serdes concepts, low-power design and optimization.

· Synthesis Tools like (DC/DC-NXT) or Fusion compiler

· Synthesis Constraints and Timing Concepts (STA)

· Spyglass (lint, DFT, PM, CLK/RST, CDC/RDC)

· Formal Verification check like Formality or Conformal LEC) Qualifications:

Education: Bachelor’s or Master’s degree in Electronics and communication Engineering or a related field.

Experience: 12 to 18 years of experience