Physical Design Engineer

As an IP Structural/Physical Design Engineer at Intel, you will join Elite IP and SoC design teams to develop next-generation Xeon products. Your role involves end-to-end IP physical design, from high-level block design to synthesis, place and route, and timing/power convergence, ensuring manufacturing-ready design databases. You will work with industry-standard tools like Synopsys Design Compiler, Cadence Conformal, and Synopsys Fusion Compiler, focusing on all aspects of RTL2GDSII flow convergence, including floor planning, power delivery, and verification.

Must Have

• Experience as a physical design engineer in the IP organization.
• Fluency in IP physical design flow (high-level block design, synthesis, place and route, timing/power convergence).
• Experience with RTL2GDSII physical design flow convergence.
• Proficiency in block-level floor planning, interconnect planning, and UPF-based power delivery methodology.
• Experience with Logic synthesis using Synopsys Design Compiler DCT.
• Experience with Formal Equivalence Verification FEV using Cadence Conformal tool.
• Experience with Auto Place-and-Route APR using Synopsys Fusion Compiler tools.
• Experience with Timing and power verification using Synopsys PrimeTime and Intel tools.
• Experience with Layout Verification and DRC analysis.
• Bachelor's Degree in Electrical Engineering, Computer Engineering, or Computer Science with at least 7+ years of experience OR Master's Degree with 6+ years of experience.
• Related field experience in CMOS circuit design and layout verification.
• Experience with industry standard CAD tools/flows for digital design.

Good to Have

• Experience in Fusion Compiler / Primetime Process and Design co-optimization for Density/Performance improvements.
• Experience in RTL based power estimation and optimization.
• Experience in CPU/ASIC design methodology and flow development, particularly in RLS, Structural Design, APR, and low power optimization domains.
• Unix skills.
• Programming skills in Python, Perl Script, and shell scripting.
• Good understanding of overall CPU/SOC design cycle and requirements.
• Experience in working on high frequency designs and methodologies.
• Willingness to multi-task and flexibility to work in a global environment.
• Good communication skills and self-motivation.
• Good analytical and Problem solving skills.
• Experience in leading small teams to design IPs.

Perks & Benefits

• Competitive salary and financial benefits such as bonuses, life and disability insurance.
• Opportunities to buy Intel stock at a discounted rate, and Intel stock awards.
• Excellent medical plans, wellness programs, and amenities.
• Time off, recreational activities, discounts on various products and services.

Job Description:

• As an IP Structural/Physical Design Engineer, you will be working alongside Elite IP and SoC design teams to deliver next-generation Xeon products and related IPs for Server markets. We are looking for candidates with experience as physical design engineers as part of the Structural Design Expert Team in the IP organization.
• You will be fluent in all aspects of IP physical design flow from high-level block design to synthesis, place and route and timing and power convergence to build a design database that is ready for manufacturing. Your responsibilities will include all aspects of RTL2GDSII physical design flow convergence including but not be limited to: Oversees definition, design, verification, and documentation for SoC (System on a Chip) development.
• Block-level floor planning, interconnect planning and UPF based power delivery methodology. Logic synthesis of design blocks using Synopsys Design Compiler DCT- Formal Equivalence Verification FEV using Cadence's Conformal tool.
• Auto Place-and-Route APR using Synopsys Fusion Compiler tools. Timing and power verification using Synopsys PrimeTime as well as Intel tools. Layout Verification and DRC analysis. What we offer: We give you opportunities to transform technology and create a better future, by delivering products that touch the lives of every person on earth.
• As a global leader in innovation and new technology, we foster a collaborative, supportive, and exciting environment where the brightest minds in the world come together to achieve exceptional results. We offer a competitive salary and financial benefits such as bonuses, life and disability insurance, opportunities to buy Intel stock at a discounted rate, and Intel stock awards (eligibility at the discretion of Intel Corporation).
• We provide benefits that promote a healthy, enjoyable life: excellent medical plans, wellness programs, and amenities, time off, recreational activities, discounts on various products and services, and much more creative perks that make Intel a Great Place to Work. We're constantly working on making a more connected and intelligent future, and we need your help. Change tomorrow. Start today.

Qualifications:

• Candidate must have a Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, with atleast 7+ years of experience listed below. OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, with 6+ years of experience listed below.
• Related field experience in CMOS circuit design, and layout verification. Industry standard CAD tools/flows for digital design.

Preferred Qualifications:

• Experience in Fusion Compiler / Primetime Process and Design co-optimization for Density/Performance improvements, RTL based power estimation and optimization.
• Experience in CPU/ASIC design methodology and flow development, particularly in the RLS, Structural Design, APR and low power optimization domains.
• Unix skills, programming skills in Python, Perl Script and shell scripting.
• Good understanding of overall CPU/SOC design cycle and requirements.
• Experience in working on high frequency designs and methodologies.
• Candidate should be willing to multi-task and flexibility to work in a global environment.
• Good communication skills and have self-motivation.
• Good analytical and Problem solving skills.
• Experience in working on high frequency designs and methodologies.
• Experience in leading small teams to design IPs.

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Additional Locations:

Business group:

The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness that power Intel’s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.