Product Engineering Intern - Genus Synthesis Solution
6 Minutes ago • All levels
Product Management
Job Description
Cadence is seeking a highly motivated MS student for a 3-month Product Engineering internship. The intern will collaborate with the R&D team on Cadence’s Genus Synthesis Solution, focusing on evaluating and improving the logic synthesis tool to optimize Power, Performance, and Area (PPA) for advanced digital ASICs. This role involves analyzing new features, addressing physically aware synthesis challenges, and supporting internal teams and customers.
Good To Have:
- Academic or past work experience in EDA, logic synthesis, physical design, or timing closure.
- Familiarity with Cadence tools such as Genus and Innovus.
- Exposure to advanced process nodes (7nm and below).
- Experience or interest in AI applications and agentic frameworks.
Must Have:
- Currently enrolled in an MS program in Electrical Engineering, ECE or Computer Engineering with a focus on VLSI design in a U.S. university.
- Strong understanding of HDLs (Verilog/SystemVerilog), logic design, and timing analysis.
- Proficiency in scripting languages such as Perl/Python, Tcl, or shell scripting.
- Strong analytical and debugging skills, with the ability to perform root-cause analysis and communicate findings effectively.
- Collaborate with the Product Engineering team to evaluate and improve Genus.
- Analyze and validate new features within Genus.
- Explore and address challenges in physically aware synthesis.
- Support internal teams and customers by troubleshooting tool usage.
We are seeking a highly motivated MS student currently enrolled in a U.S. university for a 3 month internship with our Product Engineering team. This role offers a unique opportunity to work closely with the R&D team on Cadence’s industry-leading Genus Synthesis Solution, contributing to the evolution of synthesis and place & route technologies.
Key Responsibilities
- Collaborate with the Product Engineering team to evaluate and improve Genus, a logic synthesis tool used to optimize Power, Performance, and Area (PPA) for advanced digital ASICs.
- Analyze and validate new features within Genus, ensuring correctness and identifying optimal configurations.
- Explore and address challenges in physically aware synthesis, bridging the gap between logic synthesis and place & route.
- Support internal teams and customers by troubleshooting tool usage and providing first-line feedback to R&D.
- Contribute to the interoperability of Genus with other Cadence digital implementation tools.
- Assist in documenting Product Requirement Specifications (PRS) for new features based on internal and external feedback.
Preferred Qualifications
- Currently pursuing an MS in Electrical Engineering, ECE or Computer Engineering with a focus on VLSI design.
- Academic or past work experience in EDA, logic synthesis, physical design, or timing closure is a plus.
- Familiarity with Cadence tools such as Genus and Innovus is a plus.
- Exposure to advanced process nodes (7nm and below) through coursework or projects.
- Strong understanding of HDLs (Verilog/SystemVerilog), logic design, and timing analysis.
- Proficiency in scripting languages such as Perl/Python, Tcl, or shell scripting.
- Experience or interest in AI applications and agentic frameworks is a plus.
- Strong analytical and debugging skills, with the ability to perform root-cause analysis and communicate findings effectively.
This internship is ideal for students passionate about digital design and EDA, looking to gain hands-on experience in a fast-paced, innovation-driven environment.
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