Senior Physical Design Engineer
Job Summary
Job Description
- Hands-on experience with PnR steps: Floorplanning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, Post route optimization, ECO implementation, DRC closure.
- Proficiency in high frequency design and advanced tech node implementations.
- In-depth understanding of PG-Grid optimization, including high vs low current density paths & layer/via optimization, Adaptive PDN.
- In-depth knowledge of custom clock tree, H-tree, SPINE, Multi-point CTS, and clock metrics optimization.
- Ability to tackle high placement density/congestion bottlenecks.
- In-depth knowledge of PnR tool knobs/recipes for PPA optimization.
- Experience in automation using Perl/Python and tcl.
- World-class health benefit options and coverage.
- Programs to help employees build and prepare for a financially secure future.
- Self and family resources for emotional/mental strength and resilience.
- Wellbeing programs and resources for Live+Well and Work+Well.
- Continuous learning and development programs.
- Tuition reimbursement.
- Mentorships.
7 skills required
Job Details
Job Posting Date
2025-09-04
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Company:
Qualcomm India Private Limited
Job Area:
Engineering Group, Engineering Group > Hardware Engineering
General Summary:
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.
Minimum Qualifications:
• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR
• Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
OR
• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
- 3+ years hands-on experience of different PnR steps including Floorplanning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, Post route optimization, ECO implementation and DRC closure
- Well versed with high frequency design & advanced tech node implementations
- In depth understanding of PG-Grid optimization, including identification of high vs low current density paths & layer/via optimization, Adaptive PDN experience
- In depth knowledge of custom clock tree including H-tree, SPINE, Multi-point CTS, Clock metrics optimization through tuning of CTS implementation.
- Well versed with tackling high placement density/congestion bottlenecks
- In depth knowledge of PnR tool knobs/recipes for PPA optimization
- Experience in automation using Perl/Python and tcl
- Good communication skills and ability & desire to work in a cross-site cross-functional team environment.
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