Senior Staff Physical Design Manager

Marvell is seeking a Senior Staff Physical Design Manager for its Santa Clara, CA office. This role involves leading a team in the physical design and methodology for next-generation, high-performance processor and data center chips in advanced CMOS process technology. Responsibilities include providing technical direction, coaching, project planning, resource designation, monitoring progress, partnering with other ASIC design teams, and leading recruiting efforts. The manager will work on various aspects of the chip design process within a team of experienced engineers.

Must Have

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience or Master’s degree and/or PhD with 3-5 years of experience
• Background in ASIC or SOC development
• Physical design knowledge, from netlist handoff to GDS tape-out including floor planning, place and route, clock tree synthesis, timing closure and physical verification
• Ability to handle a wide variety of projects and technical challenges
• Diligent, detail-oriented, and able to handle assignments with minimal supervision
• Excellent written and oral communications skills
• Ability to collaborate and be effective in fast-paced environment
• Self-driven individual and with ability to partner with world-wide team

Good to Have

• Minimum 2 years of experience leading projects within semiconductor product development or tape-out cycles
• Proven track record of team mentorship for high performance
• Technical leadership of ASIC or SOC Netlist to GDS tape-out
• Experience as either top-level physical design lead, STA chip Lead or chip DFT lead
• Project management experience of ASIC or SOC
• Customer interface experience
• Experience working with a distributed team

Perks & Benefits

• Flexible time off
• 401k
• Year-end shutdown
• Floating holidays
• Paid time off to volunteer

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Group Description

The Physical Design team is located in our Santa Clara, CA office, and has a long history of successful design tapeouts in advanced process nodes. Our team is made up of both newer and more experienced engineers with a broad depth of physical design engineering experience. Being a part of our team will give you a chance to work on many different aspects of the chip design process, while working alongside some of the best engineers in the industry. In this unique role, you’ll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor and data center chips in a leading-edge CMOS process technology.

What You Can Expect

• Provide technical direction, coaching, and mentoring to employees on your team and others when necessary to achieve successful project outcomes
• Assist in planning and designating project resources, monitor progress, and keep stakeholders informed the entire way
• Partner with other ASIC design teams to ensure project success
• Possibility of being management interface to ASIC customers
• Lead recruiting efforts at local universities and hiring of experienced engineers

What We're Looking For

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience or equivalent professional experience in lieu of a formal degree
• Must have a background in ASIC or SOC development
• Physical design knowledge, from netlist handoff to GDS tape-out including floor planning, place and route, clock tree synthesis, timing closure and physical verification
• Must be able to handle a wide variety of projects and technical challenges
• Diligent, detail-oriented, and able to handle assignments with minimal supervision
• The successful candidate will have excellent written and oral communications skills, and ability to collaborate and be effective in fast-paced environment
• Self-driven individual and with ability to partner with world-wide team

Preferred Qualifications:

• Minimum 2 years of experience leading projects within semiconductor product development or tape-out cycles. Proven track record of team mentorship for high performance.
• Technical leadership of ASIC or SOC Netlist to GDS tape-out
• Experience as either top-level physical design lead, STA chip Lead or chip DFT lead
• Project management experience of ASIC or SOC
• Customer interface experience
• Experience working with a distributed team

Expected Base Pay Range (USD)

157,170 - 235,400, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity

As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.

Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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