SOC Analog Integration/Power Delivery Engineer

Intel

Job Summary

Intel's XDC division is seeking a Senior Analog/Analog Integration/SOC Power Delivery Engineer to develop next-generation Custom SOC products. This role involves driving IP analog integration and power delivery, working on pre-silicon design, post-silicon validation, characterization, and debug. The engineer will guide the integration process from specification to tapeout, collaborate with various teams, and provide debugging support for analog functionality. This high-impact role requires expertise in analog design and problem-solving across multiple disciplines.

Must Have

  • Responsible for all aspects of IP analog integration and/or power delivery.
  • Work both pre-silicon design as well as follow the product through post silicon validation/characterization and debug.
  • Drive integration of analog and mixed signal IPs and high-speed interfaces into subsystems or analog components.
  • Support pathfinding studies in silicon development and relay feedback to silicon and packaging team.
  • Guide the integration process from specification documentation to silicon tapeout.
  • Provide debugging support for analog functionality related debugs in the product.
  • Work closely with analog IP, SoC architecture, SoC design, package, and platform design functions.
  • Bachelors’ degree in electrical engineering with 4+ years of experience or Master’s degree with 2 years or PhD degree in Electrical engineering with 1 year of experience.
  • 4+ years’ experience in Analog integration, Analog circuit design, Serdes, GPIO, Die2Die, Clocking, power delivery expertise.
  • 4+ years’ experience in Post silicon characterization/debug of analog circuits/designs or general post silicon debug of electrical failures.
  • Experience with various post silicon debug tools such as LVP, LADA, IREM.

Good to Have

  • Experience with mixed signal design
  • Experience building/running spice simulations

Perks & Benefits

  • Competitive pay
  • Stock
  • Bonuses
  • Health benefits
  • Retirement benefits
  • Vacation

Job Description

Job Description:

Are you ready to make your mark on cutting-edge technology that powers tomorrow's devices? Intel's XDC division is seeking an exceptional Senior Analog/Analog Integration/SOC Power Delivery Engineer to join our elite team developing Intel's next-generation Custom SOC products. This is a rare opportunity to work on high-impact, high-visibility projects within a self-sufficient team that operates at the forefront of semiconductor innovation.

As part of our dynamic engineering organization, you'll tackle complex challenges that directly influence the performance and capabilities of Intel's most advanced custom silicon solutions. This role offers the perfect blend of technical depth and strategic impact, where your expertise will drive critical decisions from initial design concepts through final product delivery.

Key Responsibilities:

  • Responsible for all aspects of IP analog integration and/or power delivery.
  • You will work both pre-silicon design as well as follow the product through post silicon validation/characterization and debug.
  • Drive integration of analog and mixed signal IPs and high-speed interfaces into subsystems or analog components and partners with package and platform teams on analog integration.
  • Support pathfinding studies in silicon development and relays feedback to silicon and packaging team on analog integration and tradeoffs.
  • Guide the integration process from specification documentation to silicon tapeout and provides debugging support for analog functionality related debugs in the product.
  • Work closely with analog IP, SoC architecture, SoC design, package, and platform design functions to meet the analog specification for the product.

The Ideal Candidate Should Exhibit the Following Behavioral Traits/Skills:

  • Effectively communicate, lead task forces, team player
  • Provide depth and breadth analog design and post silicon debug required.
  • Drive large task forces across multiple disciplines in solving pre-silicon design issues as well as post silicon root cause of electrical issues across every area of the SOC.
  • Possess expertise in design verification flows, packaging effects, and integration flows to resolve integration challenges involved in mixed signal designs and deliver optimum performance of the overall circuit.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

  • Bachelors’ degree in electrical engineering with 4+ years of experience or Master’s degree with 2 years or PhD degree in Electrical engineering with 1 year of experience.
  • 4+ years’ experience in one or more of the following:
  • Analog integration, Analog circuit design
  • Serdes, GPIO, Die2Die, Clocking, power delivery expertise
  • Post silicon characterization/debug of analog circuits/designs
  • General, post silicon debug of electrical failures
  • Experience with various post silicon debug tools such as LVP, LADA, IREM, etc.

Preferred Qualifications:

  • Experience with mixed signal design
  • Experience building/running spice simulations

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

Virtual US

Additional Locations:

Business group:

At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003

Annual Salary Range for jobs which could be performed in the US: $121,050.00-227,620.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. However, you must live and work from the country specified in the job posting, in which Intel has a legal presence. Due to legal regulations, remote work from any other country is unfortunately not permitted. * Job posting details (such as work model, location or time type) are subject to change.The application window for this job posting is expected to end by 11/28/2025

4 Skills Required For This Role

Problem Solving Business Strategy Team Player Game Texts

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