SOC FE integration engineer

This role involves developing logic design, RTL coding, and simulation for SoC designs, integrating IP blocks and subsystems into full chip SoCs. Responsibilities include defining architecture, performing quality checks for power, performance, area, and timing, and resolving RTL test failures. The engineer will also ensure secure development practices and collaborate with IP providers for integration and validation at the SoC level.

Must Have

• Develop logic design, RTL coding, and simulation for an SoC design.
• Integrate logic of IP blocks and subsystems into a full chip SoC.
• Participate in the definition of architecture and microarchitecture features.
• Perform quality checks in various logic design aspects.
• Apply strategies, tools, and methods to write RTL and optimize logic.
• Review verification plan and resolve failing RTL tests.
• Follow secure development practices to address security threat model.
• Work with IP providers to integrate and validate IPs at the SoC level.
• Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or STEM related field with 1+ years of relevant experience OR Master's Degree in Electrical Engineering, Computer Engineering, or STEM related field.
• 3 months experience using Verilog, System Verilog, Perl, Tcl, Python, or C/C++.

Good to Have

• Qualifying course work in IC/SoC Design or integration.
• Experience using Synopsys Coretools, VCS/Modelsim, Synopsys Design Compiler, Spyglass, or Lint.

Perks & Benefits

• Competitive pay
• Stock options
• Bonuses
• Health benefits
• Retirement programs
• Vacation
• Hybrid work model

Job Description:

• Develops the logic design, register transfer level (RTL) coding, and simulation for an SoC design and integrates logic of IP blocks and subsystems into a full chip SoC or discrete component design.
• Participates in the definition of architecture and microarchitecture features of the block being designed. Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence.
• Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
• Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
• Follows secure development practices to address the security threat model and security objects within the design. Works with IP providers to integrate and validate IPs at the SoC level. Drives quality assurance compliance for smooth IPSoC handoff.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Relevant experience can be obtained through schoolwork, classes and project work, internships, and/or work experience.

Minimum Qualifications:

• Candidate must have earned a Bachelor's Degree in Electrical Engineering or Computer Engineering or Computer Science or STEM related field with 1+ years of relevant experience
• -OR- Masters Degree in Electrical Engineering or Computer Engineering or STEM related field
• 3 months experience using following languages like Verilog or System Verilog or Perl or Tcl or Python or C/C++

Preferred Qualifications:

• Qualifying course work: Courses in IC/SoC Design or integration.
• Experience using Synopsys Coretools or VCS/Modelsim or Synopsys Design Compiler or Spyglass or Lint

Job Type:

College Grad

Shift:

Shift 1 (United States of America)

Primary Location:

US, Massachusetts, Beaver Brook

Business group:

At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003

Annual Salary Range for jobs which could be performed in the US: $90,890.00-148,080.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.