Senior SoC Design Verification Engineer

Intel is seeking a Senior SoC Design Verification Engineer to join the DDG team, which designs next-generation client microprocessors and delivers emulation models for pre-silicon verification. The role involves adding support for new features/IPs, debugging failures, developing high-level modeling for RTL components, implementing validation plans, building emulation targets, and participating in silicon debug. The ideal candidate will possess strong problem-solving, multitasking, and communication skills, and thrive in a dynamic team environment.

Must Have

• Adding support for new features/IPs into existing emulation models
• Learning architecture and microarchitecture by debugging failures to the root cause
• Developing high level (for example, C++/Python) modeling for RTL components
• Developing and utilizing various debug and validation tools and/or methodologies
• Building multiple emulation targets for an SoC
• Participating in the debug of failures on silicon
• Developing new testing strategies to detect failures on RTL models
• Performing system level validation tasks such as using evaluation boards and FPGAs
• SOC level feature enabling/debug

Good to Have

• Experience with reading and interpreting technical specs and Register Transfer Level (RTL) code
• Experience with validation or testing experience, especially in a silicon design team
• Experience with UNIX or Linux
• Experience with IA-32 assembly and/or Verilog programming experience
• Experience writing BFMs

Perks & Benefits

• Competitive pay
• Stock
• Bonuses
• Health benefits
• Retirement programs
• Vacation

Job Description:

Do Something Wonderful!

Intel put Silicon in Silicon Valley. No one else is obsessed with engineering and has a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.

Who We Are

DDG designs next generation client microprocessors. Our team delivers emulation models to enable pre silicon verification.

Who You Are

Your responsibilities will include but not be limited to:

• Adding support for new features/IPs into existing emulation models
• Learning architecture and microarchitecture by debugging failures to the root cause
• Developing high level (for example, C++/Python) modeling for RTL components
• Developing and utilizing various debug and validation tools and/or methodologies to implement validation plans with the goal being to ensure a solid design
• Building multiple emulation targets for an SoC
• Participating in the debug of failures on silicon and developing new testing strategies to detect these failures on RTL models
• System level validation tasks such as using evaluation boards and FPGAs
• SOC level feature enabling/debug
• The ideal candidate should exhibit the following behavioral traits:
• Problem-solving skills
• Ability to multitask
• Strong written and verbal communication skills
• Ability to work in a dynamic and team-oriented environment

Qualifications:

You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Qualifications could be obtained through a combination of schoolwork, classes, research, and/or relevant previous job and/or internship experiences.

Minimum Qualifications

• The candidate must have a Bachelor’s Degree in Computer Science, Computer Engineering or Electrical Engineering with 4+ years of relevant experience -OR- Master’s Degree in Computer Science, Computer Engineering or Electrical Engineering 3+ years of relevant experience -OR- PhD in Computer Science, Computer Engineering or Electrical Engineering

Preferred Qualifications

• Experience with reading and interpreting technical specs and Register Transfer Level (RTL) code
• Experience with validation or testing experience, especially in a silicon design team
• Experience with UNIX or Linux
• Experience with IA-32 assembly and/or Verilog programming experience
• Experience writing BFMs

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, Oregon, Hillsboro

Additional Locations:

Business group:

The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness that power Intel’s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003

Annual Salary Range for jobs which could be performed in the US: $139,710.00-262,680.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.