SOC Physical Design Verification Engineer - Full Time

2 Months ago • All levels • Research & Development • Undisclosed

About the job

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python

scalability

Job Description

Join a cutting-edge and well-funded hardware startup in Silicon Valley as a Silicon PDV Engineer. Our mission is to reimagine silicon and create Risc-V based computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.

Responsibilities

Develop our PDV methodology and infrastructure to enable the verification flow of large SoCs
Perform full chip integration and run the complete suite of physical verification checks
Provide guidance to the implementation teams throughout the project to enable early convergence and final closure
Interface with various internal and external design teams to ensure the high quality of their deliverables and successful integration
Work with the package and floorplan teams to define padring and bump map design
Collaborate with our technology team to define flows and integrate foundry PDK data

Requirements

Deep understanding of the challenges associated with in deep sub-micron process nodes
Hands-on experience in closure and tapeout of large hierarchical designs
Experience with industry standard physical verification tools (Siemens Calibre)
Strong scripting skills in tcl and python
Ability and taste for solving complex problems, efficient written and verbal communication, excellent organization skills
Self starter and highly motivated
Ability to work cross-functionally with various teams and be productive under aggressive schedules

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